Commit graph

7 commits

Author SHA1 Message Date
Duncan Laurie
d48d5a626b google/reef: ACPI: Move touchpad to SSDT and remove TPM
Instantiate the touchpad using the drivers/i2c/generic device driver
to generate the ACPI object in the SSDT.

There is not currently a separate wake pin for this device, this will
be added in EVT hardware.

This was tested on the reef board by ensuring that the touchpad device
continues to work in the OS.

Also remove the LPC TPM from the DSDT as it is not present.

Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15481
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02 01:18:30 +02:00
Saurabh Satija
af9f35a2ce mainboard/google/reef: Use common NHLT
Add ACPI NHLT table generation that the current hardware
supports.

Reef supports two audio codecs, Dialog 7219 for headsets
and Maxim 98357 for speakers.

Change-Id: Ie39947960c86b8f65140834e31f9ed9f1b578485
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15440
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01 03:22:04 +02:00
Furquan Shaikh
0e820ce745 mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_END
BUG=chrome-os-partner:54563

Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15293
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-22 22:21:13 +02:00
Furquan Shaikh
2c4a60da35 google/reef: Update flash size to 16MiB
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region
accordingly.

BUG=chrome-os-partner:54390

Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15191
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16 08:14:39 +02:00
Furquan Shaikh
ab90f96ba5 google/reef: Select UART_FOR_CONSOLE for reef
Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15044
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 17:21:17 +02:00
Aaron Durbin
07dd474d65 mainboard/google/reef: increase BIOS region size
An updated descriptor expands the BIOS region while descreasing
the 'device expansion region' utilized by the CSE. Update the
end region marker to reflect this new size as well as the
chromeos.fmd file which needs to be adjusted for logical boot
parition 2 requirement which resides halfway through the BIOS
region. The GBB was moved and shunk to accommodate the change.

Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14974
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-05-27 19:55:30 +02:00
Aaron Durbin
e065bb43d7 mainboard/google: add reef reference board
This adds the initial scaffolding for the reef reference board.
One big thing missing is the GPIO configuration.

Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f
Signed-off-by: Aaron Durbni <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14798
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13 22:38:53 +02:00