Commit Graph

4660 Commits

Author SHA1 Message Date
Angel Pons aa4cd73409 util/inteltool: Add 9 series PCH support
Add the PCI device IDs for 9 series PCHs.

Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08 21:03:58 +00:00
Sean Rhodes 3c3516b874 util/coreboot-configurator: Update the README
Update the README with new instructions for Debian 11 and MX Linux.

Also add the build dependencies.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-07 22:06:06 +00:00
Kacper Stojek fb9110b9e4 util/inteltool: Add support for Alderlake P in inteltool
TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P

Document number: 626817, 630094, 655258

Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 21:18:22 +00:00
Kangheui Won 5b84dfd1c1 util/amdfwtool: Generate hashes for signed AMDFW components
Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage
can pass it to PSP. The PSP will use these hashes to verify the
integrity of those signed firmwares.

BUG=b:203597980
TEST=Build Skyrim BIOS image.

Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:13:38 +00:00
Kangheui Won 3c164e13e7 util/amdfwtool: Add options to separate signed firmwares
Add support for separating signed firmwares into another CBFS. If
sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware
is signed against AMD chain of trust and will be verified by PSP. If
those firmware binaries are put outside FW_MAIN_[AB], vboot can skip
redundant verification, improving overall verification time.

BUG=b:206909680
TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS.

Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:11:13 +00:00
Karthikeyan Ramasubramanian 236245ec7d util/amdfwtool: Include the header with __packed definition
Checkpatch script recommends to use __packed instead of
__attribute__((packed)). Currently the build rule for amdfwtool does not
include the required header file with __packed definition. Update the
compiler flag to include the required header file.

BUG=None
TEST=Build amdfwtool.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:09:01 +00:00
Tom Hiller 520c8c070b util/docker/coreboot-sdk: add graphicsmagick-imagemagick-compat
edkII requires ImageMagick's `convert` to compile.  The
`graphicsmagick-imagemagick-compat` package provides `convert` without
the full ImageMagick library.

Change-Id: I8fc01526842eb408b0015c0652043c20f826a015
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-10-02 22:07:56 +00:00
Martin Roth d81debd946 util/lint: Update tools that use git to use a library
Each of the tools that used git had similar functionality. This combines
all of that into a single script that gets sourced by each.  This makes
maintenance much easier.

By doing this and updating each of the scripts to do the correct thing
if the script isn't being run in a git repository, it makes them work
much better for the releases, which are just released as a tarball,
without any attached git repository.

Change-Id: I61ba1cc4f7205e0d4baf993588bbc774120405cb
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 19:19:53 +00:00
Martin Roth 7726a7f272 util/lint: Update spelling.txt, add makefile to sort it
- Update spelling.txt with Lintian changes
- Remove words that are going to mess up code
- Add comments to the header about what words should be removed, along
with where the files
- Add Makefile to sort the list

Note that this undoes some of the sorting that Patrick introduced in
commit CB:38632 - ID: 805b291830
I just cannot reproduce his sort order, even using the script he put
into the commit message.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic131d5b08409f43eb700dcc8f125af00cff53d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64893
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 19:07:02 +00:00
Felix Held 3dfb485334 util/amdfwtool/data_parse: fix PMU subprogram/instance ID handling
The parsing of the PMU binary subprogram and instance numbers only
worked correctly for the cases where the ID in the name in the fw.cfg
file was between 0 and 9, but returned wrong results if it was between a
and f. Switch to using strtol with a base of 16 instead of subtracting
the char '0' from the char in the filename in
find_register_fw_filename_bios_dir to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-30 18:03:50 +00:00
Robert Zieba de6ecd0101 util/spd_tools: Change Mendocino to use 0x13 for LP5x memory type
Mendocino supports LP5x but currently doesn't support SPDs that use the
LP5x memory type, 0x15. This commit updates set 1 SPDs, which are
currently only used for mendocino, to use 0x13 for their memory type.

BUG=b:245509394
TEST=Generated SPDs, verified that only set 1 have changed to 0x13

Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-29 17:12:00 +00:00
Denis 'GNUtoo' Carikli b82486496d intelmetool: Add PCI ID for Bay Trail
Tested on a Dell Venue 8 Pro tablet

Change-Id: Ic8f162ea82b910082af4b4e05fa1408fd24f2c88
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-28 18:22:27 +00:00
Ritul Guru a2cb3400a6 util/amdfwtool: Add support for PSP NVRAM base addr and size
Add parameters to support adding the location and size of
the PSP NVRAM area to the PSP directory table.

Verified this change on PCO based Bilby platform.
Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 17:10:46 +00:00
Sean Rhodes 3c43301185 util/coreboot-configurator: Update legacy_8254_timer description
The help text and label for legacy_8254_timer is inverted, so update
this so that it is correct.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I866a15886d1cfd2b77094742787dee7a36a54e85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65348
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 15:13:22 +00:00
Sean Rhodes 914f50552f util/coreboot-configurator: Add RPM spec file
Add RPM spec to allow building RPMs, for both coreboot-configurator
and nvramtool, for Fedora.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I80a77d0f2246409c06e22abb229d63c4611a9fb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65346
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 15:13:07 +00:00
Sean Rhodes ed0c7f53eb util/coreboot-configurator: Update Debian dependancies
Change the control file to allow either libyaml-cpp0.6 or
libyaml-cpp0.7.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I754d3e2018ab78fcb657d313c8662313738b190a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-22 15:12:59 +00:00
Jakub Czapiga a0e36d8cba tests: Add support for tests build failures detection
This patch introduces new target: junit.xml-unit-tests, which builds and
runs unit-tests. It also creates build log containing build logs. This
feature allows for one to see build failures in Jenkins dashboard.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I94184379dcc2ac10f1a47f4a9d205cacbeb640fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67372
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-21 14:06:42 +00:00
Elyes Haouas c8870b1334 crossgcc: Upgrade llvm from version 14.0.6 to 15.0.0
Test build for QEMU x86 i440fx/piix4.

Change-Id: I3144a83fcbd92eec51d70e9be33ff2fcb2821731
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67416
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18 17:14:10 +00:00
Elyes Haouas 035e9f9f0c crossgcc: Upgrade cmake from 3.23.2 to 3.24.2
Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-18 17:14:04 +00:00
Yidi Lin 0811a6492d cbmem: use aligned_memcpy for reading lb_cbmem_entry information
The lbtable contains the memory entries that have fields unnaturally
aligned in memory. Therefore, we need to perform an aligned_memcpy() to
fix the issues with platforms that don't allow unaligned accesses.

BUG=b:246887035
TEST=cbmem -l; cbmem -r ${CBMEM ID}

Change-Id: Id94e3d65118083a081fc060a6938836f6176ab54
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-18 03:24:16 +00:00
Patrick Georgi f0d5f67e46 riscv: Enable the newfangled way of selecting instruction sets
gcc12+ will require riscv architecture selection to come not only with
featurei suffixd charactersa, it also comes with feature_ful suffix_ed
words_mith. Much creative, very appreciate.

To accommodate for this madness, enable the already existing (but off by
default) support for that in our gcc11 build, support using by detecting
the compiler's behavior in xcompile and pass that knowledge along to our
build system.

Then cross our fingers and hope for the best!

Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-17 05:56:34 +00:00
Elyes Haouas 3541c31add util/kconfig/regex.c: Remove leftover
coreboot doesn't support the MIPS architecture anymore.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I404d034949a7786d7971117081537baf27ff2e22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-16 14:52:44 +00:00
Elyes Haouas a3c287d7a3 crossgcc [binutils]: Remove 'enable-plugins' option
unneeded 'enable-plugins' option sneaked in..., so remove it.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id1d7f2c7e6b70c28e1060c6ee915363ffe412ef6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 13:06:22 +00:00
Elyes Haouas b8e5baf2f2 crossgcc [binutils]: Remove invalid enable-interwork option
'enable-interwork' is not a binutils configure option.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I29cd6137c700ff6871868a723daf33909aa218ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65609
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 13:05:44 +00:00
Nico Huber c0fc38eed8 sconfig: Allow to specify device operations
Currently we only have runtime mechanisms to assign device operations to
a node in our devicetree (with one exception: the root device). The most
common method is to map PCI IDs to the device operations with a `struct
pci_driver`. Another accustomed way is to let a chip driver assign them.

For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
ID lists grew very large and are incredibly error-prone. Often, IDs are
missing and sometimes IDs are added almost mechanically without checking
the code for compatibility. Maintaining these lists in a central place
also reduces flexibility.

Now, for onboard devices it is actually unnecessary to assign the device
operations at runtime. We already know exactly what operations should be
assigned. And since we are using chipset devicetrees, we have a perfect
place to put that information.

This patch adds a simple mechanism to `sconfig`. It allows us to speci-
fy operations per device, e.g.

  device pci 00.0 alias system_agent on
          ops system_agent_ops
  end

The operations are given as a C identifier. In this example, we simply
assume that a global `struct device_operations system_agent_ops` exists.

Change-Id: I2833d2f2450fde3206c33393f58b86fd4280b566
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15 13:06:47 +00:00
Jeremy Compostella e1465e2157 util/ifittool: Error out if microcodes do not fit the FIT table
parse_microcode_blob() returns success when it reaches max_fit_entries
microcode. It makes the FIT table size verification in
fit_add_microcode_file() useless. This patch makes
parse_microcode_blob() error out if max_fit_entries is reached.

Note that this size verification is critical as a FIT table only
partially listing the microcode patches can lead to boot failures as
recently observed on Raptor Lake-P.

BRANCH=firmware-brya-14505.B
BUG=b:245380705
TEST=compilation errors out when trying to stitch more than
     CONFIG_CPU_INTEL_NUM_FIT_ENTRIES microcode patches.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67454
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
2022-09-15 13:01:42 +00:00
Matt DeVillier 275a9a3d7e util/lint: Add a check for touchpads using the "probed" flag
As of commit 2cf52d80a6 ("mb/*/{device,override}tree: Set touchpads to
use detect (vs probed) flag") all touchpads in the tree have been
switched from using the 'probed' flag to 'detect.' Add a lint check to
ensure no touchpads are added with the probed flag.

TEST=manually change one touchpad to use 'probed' flag and ensure lint
check catches it.

Change-Id: Ie0aee2e3778fc56c6c21c97995738a147a1fa0d4
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67486
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14 20:52:02 +00:00
Elyes Haouas 8de4d27810 crossgcc: binutils: Remove invalid enable-multilibs option
Looks like somewhere after the original implementation it was renamed to
--enable-multilib without the s.
'enable-multilibs' is not a valid option for binutils.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I105cc9fa489aed24905dedb785c70bc69ed18970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65608
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-14 17:13:02 +00:00
Maxim Polyakov 593b0f1f23 intelp2m: Add Go Managing Dependencies System support
Add go.mod containing the full name of the project according to the
docs [1]: review.coreboot.org/coreboot.git/util/intelp2m, and also,
based on this, rename the internal packages to point to the absolute
path. This will allow Go Managing Dependencies System to integrate
packages from intelp2m to third-party Go written on the Go language [1].
This also requires fixing the Golang compiler version in go.mod: use
go1.18 [2], the latest up-to-date version.

[1] https://web.archive.org/web/20220910100342/https://go.dev/doc/modules/managing-dependencies
[2] https://web.archive.org/web/20220910100206/https://tip.golang.org/doc/go1.18

[ TEST ]
1) Import the coreboot project into some go project:

$cd path/to/go-project
$go get review.coreboot.org/coreboot.git
go: downloading review.coreboot.org/coreboot.git v0.0.0-20220903004133
-39914a50ae16
go: added review.coreboot.org/coreboot.git v0.0.0-20220903004133
-39914a50ae16

Thus, 'go get' correctly downloaded the contents of the repository.

2) Import intelp2m:

$cd path/to/go-project
$go get review.coreboot.org/coreboot.git/util/intelp2m
review.coreboot.org/coreboot.git/util/intelp2m imports
	./config: "./config" is relative, but relative import paths are
not supported in module mode
review.coreboot.org/coreboot.git/util/intelp2m imports
	./parser: "./parser" is relative, but relative import paths are
not supported in module mode

Thus, the problem is in the package names, but after this patch, the
import should be without errors.

3) Import a repository with an incorrect url:

$cd path/to/go-project
$go get review.coreboot.org/coreboot/test
go: unrecognized import path "review.coreboot.org/coreboot/test":
reading https://review.coreboot.org/coreboot/test?go-get=1:
404 Not Found

This has not happened in previous cases.

Change-Id: I12efae31227129b8c884af10fb233f398c4094e7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-09-12 12:55:05 +00:00
Jeremy Compostella 46ffccd753 util/ifittool: Fix buffer overflow with padded microcode patches
Some microcode patches are padded with zeros, which make
parse_microcode_blob() read beyond the end of the buffer.

BRANCH=firmware-brya-14505.B
BUG=b:245380705
TEST=No segmentation fault with a padded microcode patch

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67460
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-12 12:33:36 +00:00
Martin Roth 38bbff47a7 util/lint/lint: Add -I option to invert test results
To test the linters, we want to invert the results so that any test that
passes shows up as a failure. This will allow us to verify that all of
the linters are working correctly.

This will be tested nightly as well as on changes to the lint tools.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-07 22:35:02 +00:00
Caveh Jalali c762e231da util/spd_tools: Update LP5X support for ADL/RPL/MTL
This updates the SPD utility and generated SPDs for LP5X to use memory
type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on
Intel Tech Advisory Doc ID #616599 dated May 2022, page 15.

SPDs were regenerated with:
  "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5"

This only affects the SPDs for 2 memory parts for Intel SoCs and the
only board referencing these is rex.

BUG=b:242765117
TEST=inspected SPD hex dump

Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07 22:19:21 +00:00
Elyes Haouas 0d42db666b lint/checkpatch: Fix incorrect camelcase detection on numeric constant
This reduce the difference with linux v6.0-rc3.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I15e1a935665c38b8a2109d412b1d16f935cbb402
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-06 17:59:55 +00:00
Martin Roth f6ba75c736 util/lint/lint-stable-019-header-files: add test
Add a test to make sure that the linter fails correctly.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I971951d4248dd10abe4c622025fdaf86e014c6cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06 17:58:57 +00:00
Martin Roth cd9110b6d2 util/lint: Add rules.h & compiler.h to 019-header-files linter
The rules.h & compiler.h includes were removed in previous commits, so
add the checks to keep them out to the linter.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06 17:58:31 +00:00
Martin Roth 8a3f5a1d0b util/lint: ignore util/goswid, a new submodule
git submodules should be ignored when parsing the coreboot tree for
lint errors. Those should be handled in their own commit checks.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I62b58f0c536312fe4677855bca8f44bc7d3ebc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-05 19:38:12 +00:00
Karthikeyan Ramasubramanian 0dd3cf4534 util/amdfwtool/amdfwread: Fix incorrect option index
index I/O argument to getopt_long is not the index to argv. Instead it
is an index into the optlong array corresponding to the parsed option.
Also getopt() uses a global variable optind to track the index of the
next argument to be processed. Use the optindex variable as an index to
extract the filename from argv.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Change-Id: I33c74a0c8e12c5af76954524cf7294b7541d286b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66553
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04 17:06:21 +00:00
Caveh Jalali 7dd42da9a0 util/spd_tools: Rebuild utils when source changes
This adds source file dependencies to utilities so that they are rebuilt
when the source is changed. Previously, binaries were only built if they
did not already exist and never rebuilt to reflect source file changes.

BUG=none
TEST=verified binaries are rebuilt when source files are touched.

Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-04 16:57:33 +00:00
Martin Roth d12e4f5088 util/lint: Add lint tests to make sure they fail correctly
Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-04 16:43:50 +00:00
Martin Roth 8b45c1244e util/lint/lint: Reformat usage
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I684d374bd02a42e178383c26936e137e173f8f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-03 23:50:15 +00:00
Martin Roth 8ea8d856f3 util/lint/lint: Add command line parsing
The lint script just did very basic argument parsing and required the
sub-command and --junit argument to be in specific locations.  I'm
adding additional commands, so the first step is to add true command
line parsing.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7118c29e6c5d785b35a7ae12cf5984c43ebc3ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67191
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-03 23:49:53 +00:00
Julius Werner d96ca24652 cbfs/vboot: Adapt to new vb2_digest API
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new
hwcrypto_allowed argument, to potentially let them try to call the
vb2ex_hwcrypto API for hash calculation. This change will open hardware
crypto acceleration up to all hash calculations in coreboot (most
notably CBFS verification). As part of this change, the
vb2_digest_buffer() function has been removed, so replace existing
instances in coreboot with the newer vb2_hash_calculate() API.

Due to the circular dependency of these changes with vboot, this patch
also needs to update the vboot submodule:

Updating from commit id 18cb85b5:
    2load_kernel.c: Expose load kernel as vb2_api

to commit id b827ddb9:
    tests: Ensure auxfw sync runs after EC sync

This brings in 15 new commits.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02 23:51:29 +00:00
Felix Singer b45b48de73 util/docker/coreboot-jenkins-node: Install cmocka
flashrom uses cmocka for unit testing. Install it so that the CI can
use it.

Change-Id: I5c168e480d6f4cbfbbd175ecb035c88bfcbac00b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67272
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02 18:48:13 +00:00
EricKY Cheng 20f092d339 util/spd_tools: Add AMD Mendocino (MDN) platform
This patch adds support for MDN platform to the spd_tools.
This change replaces SBR with MDN.

BUG=b:243337816
TEST=Able to generate SPD for LP5 DRAM part.

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: If099af36de8a64e96fbfde32eaf15990f4b330c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-30 14:53:05 +00:00
Zheng Bao c88f2b5be7 amdfwtool: Fix indentation
Change-Id: I4c57c9bade318d54315f9692cd37edb694e33aa9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58320
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29 22:52:59 +00:00
Martin Roth 2dd74906e4 util/futility: Ignore deprecated declarations in OpenSSL 3.0
Building futility with OpenSSL 3.0 (default in latest Debian sid)
results in a number of warnings that various declarations have been
deprecated.  Since we (and futility) have warnings as errors enabled,
this causes the building of futility to fail, killing the entire
coreboot build.

To work around this until futility is updated, turn off the warnings
about deprecated declarations.

Bug 243994708 has been filed to get futility updated.  This workaround
can be removed when futility builds cleanly with the latest libsssl-dev.

BUG=b:243994708
TEST=Futility build doesn't fail with libssl-dev > 3.0

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I54e27e09b0d50530709864672afe35c59c76f06e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
2022-08-29 18:34:18 +00:00
Felix Singer feab41b030 util/docker/coreboot-sdk: Install GNAT 12
For some reason GNAT 11 is not able to build GNAT 12, since there are
some Ada errors during the compilation. However, it works with GNAT 12.
So use GNAT 12 for the host toolchain instead.

Change-Id: If00a05a0c8564e624809268a12fae28261e380a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-27 16:01:52 +00:00
Felix Singer acbdc4d72e util/docker/coreboot-sdk: Replace package qemu with qemu-system
The qemu package doesn't exist anymore or it was renamed. Instead of
installing QEMU for all available architectures, install only the
packages which ship architectures that are supported by coreboot.

  * qemu-system-arm
  * qemu-system-misc (for RISC-V)
  * qemu-system-ppc
  * qemu-system-x86

Change-Id: Ifc46a8c9fcb1ab3c38dc8cbbc906882e93a719d7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-27 16:01:12 +00:00
Tom Hiller a0eb855ef4 util/docker/coreboot-sdk: Remove doxygen
Doxygen was removed at the project level.  Remove the doxygen Debian
package and make target.

Change-Id: Ib82ba7890e7f53357eeca318b5f844164747aecd
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67039
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27 15:50:50 +00:00
Ritul Guru 9a321f31c8 util/amdfwtool: Add changes to reserve BIOS SIG
changes to reserve space for AMD_BIOS_SIG when
BIOS image is signed with RTMSignature.

Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-26 16:04:51 +00:00