GNUBoot/coreboot-kgpe-d16
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8 commits

Author SHA1 Message Date
Zheng Bao
795d73c6d8 soc/amd/picasso: Update coreboot UPD variable names to include units 
Use command below to change the variable globally.

sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
   --exclude-dir=build --exclude-dir=crossgcc`

BUG=b:171334623
TEST=Build

Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2020-11-06 13:02:24 +00:00
Kevin Chiu
cdd9f5cb72 soc/amd/picasso: Add THERMCTL_LIMIT DPTC parameter support 
Add THERMCTL_LIMIT (die temperature limit) DPTC parameter
for clamshell/tablet mode.

BUG=b:157943445
BRANCH=zork
TEST=build

Change-Id: Id193a74210c92d1e45ed4824ee9c0fc9ceaa5e3a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-09-20 17:24:40 +00:00
Chris Wang
4735b1c01b soc/amd/picasso: add dptc support 
add dptc support for different power parameter on tablet/clamshell mode

The BIOS may choose to adjust power and/or thermal parameters at its own
discretion. The DPTC interface(DPTCi) ALIB Function adds flexibility by
allowing  the BIOS to request power state changes independently of specific
 events.

BUG=b:157943445
BRANCH=none
TEST=Build.Generated ASL code from SSDT by acipgen_dptci().check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-09-17 06:05:27 +00:00
Marshall Dawson
39c64b0bdd soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP 
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot.  Do the same
for the northbridge's IOAPIC base address.

Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.

BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-10 12:37:45 +00:00
John Zhao
f6f1f734ee soc/amd/picasso: Avoid NULL pointer dereference 
Coverity detects dereferencing a pointer that might be "NULL" when
calling acpigen_write_scope. Add sanity check for scope to prevent
NULL pointer dereference.

Found-by: Coverity CID 1429980
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I6214fb83bccb19fe4edad65ce6b862815b8dcec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42837
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-10 17:33:39 +00:00
Felix Held
3858fb121e soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdt 
Found-by: Coverity CID 1429980

Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2020-06-29 16:04:27 +00:00
Furquan Shaikh
bc45650b5f soc/amd/picasso: Place early stages and data buffers at the bottom of DRAM 
This change updates memlayout.ld for Picasso to place all early
stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot
workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at
the bottom of DRAM starting at 32MiB. This uses static allocation for
most components by defining Kconfig variables for base and size. It
relies on the linker to complain if any of the assumptions are broken.

This also allows romstage to use linker symbols for
_early_reserved_dram and _eearly_reserved_dram to store information in
CBMEM about the early DRAM usage by coreboot before ramstage starts
execution. This allows ramstage to reserve this memory region in BIOS
tables so that S3 resume can reuse the same space without corrupting
OS memory.

BUG=b:155322763
TEST=Verified memory reported by coreboot:
Writing coreboot table at 0xcc656000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-0000000001ffffff: RAM
 4. 0000000002000000-000000000223ffff: RESERVED
 5. 0000000002240000-00000000cc512fff: RAM
 6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES
 7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE
 8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES
 9. 00000000cd800000-00000000cfffffff: RESERVED
10. 00000000f8000000-00000000fbffffff: RESERVED
11. 0000000100000000-000000042f33ffff: RAM
12. 000000042f340000-000000042fffffff: RESERVED

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2020-06-13 06:50:51 +00:00
Marshall Dawson
eb72487784 soc/amd/picasso: Add pcie root complex driver 
* Declare memory and reserved areas using HOBs for regions above top
  of low memory.
* Copy northbridge_fill_ssdt_generator from stoneyridge.

BUG=b:147042464
TEST=Boot trembyle and see PCI resources in the log:
   PCI: 00:00.0
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
   PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
   PCI: 00:00.0 resource base 100000 size cd700000 align 0 gran 0 limit 0 flags e0004200 index 3
   PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   PCI: 00:00.0 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 4
   PCI: 00:00.0 resource base 100000000 size 12f340000 align 0 gran 0 limit 0 flags e0004200 index 5
   PCI: 00:00.0 resource base 22f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 6
   PCI: 00:00.0 resource base cd800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 7
   PCI: 00:00.0 resource base cd7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 8
   PCI: 00:00.0 resource base cc7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 9
   PCI: 00:00.0 resource base 1090000 size b0000 align 0 gran 0 limit 0 flags f0004200 index a

Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-05-20 00:31:01 +00:00