Commit graph

13 commits

Author SHA1 Message Date
Marc Jones
33eef1374f soc/amd/stoneyridge: Add RunOnAP support
Add support for AGESA callbacks RunFcnOnAp() and RunFcnOnAllAp().
Update the wording on the AP errors. The functions are not missing,
they are not supported.

BUG= b:66690176
BRANCH=none
TEST=Check serial output for the AP calls from AGESA.

Change-Id: Id30cb2e0c6cc474158f3a7710dbb8ecf54f1ffe4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-02 03:15:45 +00:00
Martin Roth
4f92b15c13 amd/stoneyridge: Update def_callouts.c to reset using reset.c
Convert functionality to use coreboot-centric functions and defined
values.  This change should have no functional effect.

BUG=b:62241048
TEST=Build Gardenia; Build & boot Kahlee.

Change-Id: I62ae50af05d3ac770560368245c4ae81cf9c4395
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-01 03:29:28 +00:00
Martin Roth
b2c0d08a4e soc/amd/common: Remove direct AGESA header includes
All AGESA headers should be included only through agesawrapper.h

BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee

Change-Id: I94140235f46a627dda99540af8619aeca3f4f157
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14 21:00:02 +00:00
Marc Jones
6e70d67824 soc/amd/common: Add weak call for platform PCIE slot reset
Since it is fairly uncommon, add a weak call that may be done by
the platform if it has the support.

BUG=b:66690176
BRANCH=none
TEST=coreboot builds.

Change-Id: I50008da6f85039a428184bf9e7642c0aa6610247
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31 02:22:02 +00:00
Marc Jones
bb59f67ee8 soc/amd/common: Remove agesa_LateRunApTask() callback
agesa_LateRunApTask() is not a callback, but a AGESA call. This is a mistake
in the AGESA spec and the function is in the wrong section.

bug=b:66690176, b:67210418
branch=none
test=none

Change-Id: I900e7db13a58e73a7b054e06088bc77c89445876
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-27 16:58:45 +00:00
Martin Roth
c450fbe909 Stoney Ridge Platforms: Make AGESA callout tables common
There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.

Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd

Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.

Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4.  A bug has been filed for support for
the upcoming Grunt platform.

BUG=b:67209686
TEST=Build and boot on Kahlee

Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-20 17:48:37 +00:00
Marc Jones
7e710e047f amd/soc/common: Print an error if an AGESA callout isn't supported
Let the developer or user know that a callout isn't supported.

Change-Id: I73a6c6930a6661627ad76e27bbb78be99e237949
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 22:33:37 +00:00
Marc Jones
4f886cc19a amd/stoneyridge: Make all AGESA reset requests immediate
The AGESA RESET_WHENEVER request were never doing a reset in coreboot.
We don't have a way to collect a whenever and reset at some later time,
so just do the reset immediately.

BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.

Change-Id: If2654ec0c5c5dbdcea6fc9374371c3388d29fdc7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21978
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-13 16:48:33 +00:00
Martin Roth
f80a431c11 soc/amd/common: Add framework for missing AGESA callouts
These are required callout functions that currently are not implemented.
agesa_LateRunApTask does not seem to be called, but the others are.

BUG=b:66690176
TEST=Build Kahlee.  Tested in next commit.

Change-Id: Iee5f9c4847a5309a25045fca8c73be4f811c281a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21707
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:24:49 +00:00
Marc Jones
dfeb1c4da9 stoneyridge: Rename hudson to southbridge
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.

BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.

Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-14 14:50:51 +00:00
Marshall Dawson
f3dc71e031 soc/amd/common: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the
remaining ones as todo.  Some of the lines requiring a >80
break are indented too much currently.

Changes to agesawrapper.c cause the build to change, so this
file is also left as-is.  Make hex values consistently lower-case.

BUG=chrome-os-partner:622407746

Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27 20:51:39 +00:00
Stefan Reinauer
8d29dd1258 vendorcode/amd: Unify Porting.h across all targets
This requires to also unify the calling convention for
AGESA functions from
 AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
 AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)

On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.

Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27 17:35:39 +00:00
Marc Jones
1587dc8a2b soc/amd/stoneyridge: Add northbridge support
Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.

Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile

Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26 00:46:18 +00:00