Both mainboards have the same documentation. Instead of having two list
items referring to the same document, just merge the two items.
This fixes the following Sphinx warning:
WARNING: duplicated entry found in toctree: mainboard/lenovo/w530
Change-Id: I4140b34db01b1d5f47a39b9c1e33405e7789de63
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77503
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The document for northbridge/intel/i440bx doesn't exist and it didn't
exist at the time of introduction of these two mainboard documents. So
replace the reference with just the northbridge name.
This fixes the following Sphinx warning:
WARNING: unknown document: '../../northbridge/intel/i440bx/index'
Change-Id: Iaa67399f9d0e62d5d54ae08f5ebb8c70073c601f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Add new documentation generated by util/util_readme/util_readme.sh.
This also fixes the following Sphinx warning:
util/abuild/index.md: WARNING: document isn't included in any toctree
Change-Id: I26c33af3c5a5853f6bcce23e982a6b192b01f1d7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Sections may not start with transitions. Remove them.
This fixes the following Sphinx error:
ERROR: Document or section may not begin with a transition.
Change-Id: I519af83df14e44b0709dee7e338dba1ee6413f0a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77440
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clevo started using OZ711LV2 for the SD card reader around the time of
making its TGL boards. Without the driver, CPUs don't go to power states
lower than C2 due to LTR not being programmed. After enabling the driver
the CPU will go to C8 while the system is idle, giving significant power
savings if the system is left on battery power.
There is another issue with RPL where it only goes to C6 instead of C8.
This may be due to the intel_idle driver in Linux (as of 6.5-rc6
mainline and 6.4.6 stable) not supporting RPL C-states.
- tgl: Started being used with the Gazelle 3060 variant
- adl: Used on all models
- rpl: bonw15 does not have an SD card reader
Change-Id: I85c60feb6dcae7d877e70a6c6f2d3a7b3296fa0e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The psp_transfer.h file was the same under all SoCs, and is really
tied to the file common/vboot/transfer.c, not the SOC.
This patch makes an include directory under vboot to put the header into
and sets it to be included for all SoCs using SOC_AMD_COMMON. This makes
the header file available to all platforms, so that new chips that don't
use the psp_verstage don't have to make a psp_transfer.h file just to
satisfy the compiler.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b9f2adee3a1d4d8d32813ec0a850344b7d717b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77303
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
License classifiers are much better about classifying files with SPDX
headers than they are at classifying the general text licenses due to
minor variations in the text. To help with classification, add the
SPDX headers to the files.
To see the current state of coreboot's licensing, see:
https://coreboot.org/fossology/
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If490f6705e7862d9ad02c925104113b355434101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new block for handling overclocking watchdog. The watchdog is
present since Skylake or maybe even earlier so it is safe to use with
most of the microarchitectures utilizing intelblocks.
The patch adds the common block for initializing and feeding the
watchdog. Timeout is defined statically in Kconfig and should be set
high enough by the board or SoC Kconfig to let the board boot with
full memory training and avoid reset loops. Full training of 128GB
DDR5 DIMM memory on AlderLake takes about 5 minutes. Newer SoCs
with newer memory technologies and higher RAM capacity may take more.
The default has been set to 10 minutes.
The patch also adds support for feeding watchdog in driverless mode,
i.e. it utilizies periodic SMI to reload the timeout value and restart
the watchdog timer. This is optional and selectable by Kconfig option
as well. If the option is not enabled, payload and/or software must
ensure to keep feeding the watchdog, otherwise the platform will
reset.
TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets
after some time. Enable the watchdog in driverless mode and see the
platform no longer resets and periodic SMI keeps feeding the watchdog.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68944
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new memory part in the mem_parts_used.txt and generate the
SPD ID.
1. MICRON MT62F512M32D2DR-031 WT:B
BUG=b:291018417
TEST=emerge-rex coreboot
Change-Id: I6e05c0d41a4899ed64dbab7efd8904cd361cb50e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77426
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the schematic, karis does not have a WWAN module, remove
related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch changes the SAR table selection logic to use FW_CONFIG which
will eventually help to support different WiFi SAR tables.
TEST=Able to build and boot google/rex.
Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de
Signed-off-by: YH Lin <yueherngl@google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These Kconfig options were being used basically as #define statements,
which is unnecessary. This isn't a good use of Kconfig options and would
be better just as #defines if actually needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This patch moves the line adding hwlib to the include path to the inner
makefile so that it doesn't get added to every build, but only when
CONFIG_USE_SIEMENS_HWILIB=y
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id668b76366a554efff560cec746e637487ebdbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77417
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This keeps the vc/amd/pi & pi/00670F00 Makefiles from getting pulled
into the build when they aren't needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If600c78c2ba74dd03cf493586dae037b96b7d623
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This change tells the build to only pull vc/eltan/security/Makefile.inc
into the overall build when USE_VENDORCODE_ELTAN is enabled in Kconfig.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1e462d8cc21c44716463c41cab598588cf4a22c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77418
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage.
BUG=b:296511904, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified by EE
Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Scaleway Tagada was removed with commit c013fa6234 and Intel Galileo was
removed with commit 037c25d4dd. So remove their configs.
Change-Id: I1c491f437b8a1104bdf31a34e3c7d2c4e5794301
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77415
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tweak a few sentences noticed when reading this.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0a072c83402bc551a6bbdb7cd7c55fc3505784b2
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77464
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: Patrick Georgi <patrick@coreboot.org>
This is a useful feature, so add a note about it.
Change-Id: If29f6480f878bdaf877dc208cc4861b884e10840
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77465
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Update the U-Boot version to the latest release. Also switch to github
since it is typically much faster to download than the existing URL.
Drop the 'experimental' tag since this payload is pretty stable. It is
also tested regularly in U-Boot's CI.
Change-Id: I082130539c3474593a82e4b21cb995380f4db168
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77463
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
We only checked that the resource fits below the given `limit` in
memranges_find_entry(), but then accidentally placed it at the top
of the found memrange. As most resources have only a coarse limit,
e.g. the 4G barrier of 32-bit space, this became only visible when
artificially setting an unusual, lower limit on a resource.
So, for the final placement, use `MIN(limit, range end)` instead
of the range's end alone.
Change-Id: I3cc62ac3d427683c00ba0ac9f991fca62e99ce44
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Set customized_leds value for RTL8111K to fix led can't work.
BUG=b:297093096
BRANCH=firmware-brya-14505.B
TEST=Verified RTL8125 and RTL8111K led can work normally.
Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the nokris variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:285838647
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOKRIS
Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
In order to support logging of events for PSR data backup command
status during CSE firmware downgrade, add support for
ELOG_TYPE_PSR_DATA_BACKUP and ELOG_TYPE_PSR_DATA_LOST types.
BRANCH=None
BUG=b:273207144
TEST=Verify event shows in eventlog after CSE firmware downgrade
Change-Id: Ibb78ac8d420bb7a64328ce009ddcb99030519ec6
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77005
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Add new eventlog types to support logging of Platform Service Record
(PSR) backup related messages. Eventlog entries are added on PSR data
backup success/failure and also when PSR data is lost.
BRANCH=None
BUG=b:273207144
TEST=Verify elog event added after PSR data backup command is sent
cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent
...
ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC
Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `use_8254` should be flipped, the same as the other Intel
SOCs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Joxer will have SKUs with no type-c on daughter board, add fw_config
for EC control it.
BUG=b:297131468
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command
00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0
00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1
Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Fix regression introduced in I25e757108e0dd473969fe5a192ad0733f1fe6286
"payloads/external/LinuxBoot: Clean up".
Include the initrd into the payload. Allows to actually use LinuxBoot.
Change-Id: I5ab6b1a43a4100e83f4c188b9ea3451ab7b4ffe5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77412
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile
SoCs have, so add the additional 3 SMN base address definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When LZMA compression is selected, then it's not needed to check if LZ4
compression is selected in addition. So instead of handling both cases
separately, check for LZ4 only if LZMA is not selected.
This applies to the cases of both, FSP-M and FSP-S.
Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
To avoid redundancy about how to call into `Makefile.sphinx`,
only do that from the `Documentation/Makefile` and call into
that from the top level.
Change-Id: I99c462cdaf83d711e4b7c07b713d304274db8cb4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Internal flashing possible
- Fix link
- Link here from the list of mainboards
- More consistent naming
Change-Id: Iaf6448c1e9f0dae9480fa9785a12f09d42f8cf7d
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77377
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with a Kingston UV500.
It works the same (3Gb/s) as with vendor FW.
According to smartctl -a /dev/sda:
SATA Version is: SATA 3.1, 6.0 Gb/s (current: 3.0 Gb/s)
Change-Id: I5c714351586e6084029ce4c54fb47cbae4d3405b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77376
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Delete this RTC from the configuration as fa_ehl mainboard
uses a different real time clock.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
The mainboard currently does not make use of a dedicated TPM.
Although it has one assembled. This TPM is not connected
via LPC hence it is turned off in the devicetree.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
fa_ehl mainboard does not make use of the SIEMENS NC_FPGA
as it is not placed on this board.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Felix Singer