The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.
Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18332
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to coreboot’s payload API [1] the magic value passed to the
payload should be 0x12345678, not 12345678. Fix that.
[1] https://www.coreboot.org/Payload_API
Change-Id: I10a7f7b1a4aec100416c5e7e4ba7f8add10ef5c5
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit makes a basic adjustment for GPIOs, device tree, flash map and
MRC settings. With these basic settings the mainboard boots into
Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow.
Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18292
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
As per BWG, CPU MP Init (loading ucode) should be done prior
to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry
(before FSP-S call).
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Boot to OS with all threads enabled.
Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18287
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The four options are only used in X86:
- BOOTBLOCK_SIMPLE
- BOOTBLOCK_NORMAL
- BOOTBLOCK_SOURCE
- SKIP_MAX_REBOOT_CNT_CLEAR
Move them all into src/arch/x86/Kconfig - this puts them in the chipset
menu instead of general setup.
Verified that this makes no significant changes to any config file.
Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17909
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
For boolean types, 'n' is the default default value - it doesn't
NEED to be set. If it IS set, it prevents a later default from
being set. So by removing the 'default n' statements from the
early symbols, they can be overridden other places in the tree.
Verified that this makes no significant changes to any config file.
Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This reverts commit 32997fb0bc.
This change is breaking I2S audio on Kabylake platforms so
revert the change to fix audio.
BUG=chrome-os-partner:61548,chrome-os-partner:61009
TEST=manual testing on Eve P1 system
Change-Id: I3212c8be83078ed57e38501386605e67b87d5bd0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18360
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Some variants need the internal pull resistor on GPIO_SSUS_40
set explicitly to pull down rather than disabling the pull,
in order for the ram-id to be read correctly via GPIO.
Correct this by adding a function to enable and set the internal pull
and define its use as needed in the board's variant.h.
Chromium source:
branch: firmware-gnawty-5216.239.B
/src/soc/intel/baytrail/baytrail/gpio.h#418
/src/mainboard/google/gnawty/romstage.c#60
Test: boot 4GB Candy board and observe correct RAM id, amount detected
Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18309
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Those are the result from tracing what linux or the option rom do
but are not needed here.
TESTED on Thinkpad X60.
Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18294
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Poppy doesn't support 8042 keyboard. Select
NO_FADT_8042 to disable 8042 in FADT header.
Kernel will not try to access 8042 region
if 8042.FADT=0
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: I00182eb4b059d4d9f0705d349dc98651e3955f0d
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/18311
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kernel relies on FADT 8042 flag to enable/disable
8042 interface. If FADT reports 8042 capability and
8042 (/PS2) capability is actually disabled by coreboot,
kernel would assume the presence of 8042 based on the
FADT flag. This results in undesired system power off when
kernel tries to access the 8042 memory region. To address
this, CONFIG_NO_FADT_8042 was added to selectively
disable 8042 on FADT.
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/18307
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update DPTF parameters based on thermal team test result.
1. Update TSR2 trigger points.
TSR2 passive point: 70, critical point: 90
2. Set PL2 Max to 15W.
BUG=chrome-os-partner:61383
BRANCH=reef
TEST=build, boot on snappy, and verified by thermal team
Change-Id: I8d01d6c1d7eabd359ceb131f3cd10965d4ac2c42
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18318
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Void pointer arithmetics are forbidden in standard C but GCC has
an extension that allows it.
Change-Id: I43029b2ab2f7709b8e1ba85eb05c31341b8ac16f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18293
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Performance degradation seen with current PL1 throttling rate as 8
seconds for TSR1 sensor with Aquarium workload. After fine tuning PL1
throttling rate to 15 seconds, fps score improved.
BUG=chrome-os-partner:60038
BRANCH=reef
TEST=Built and tested on electro system
Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/18317
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
There will be more follow-up changes.
BUG=chrome-os-partner:62377
BRANCH=None
TEST=emerge-scarlet coreboot libpayload
Change-Id: I9ca45598ff0ab12bf8063d16a86be564cf509390
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a020a9ba1228b15599e202972df0096f58b1b31c
Original-Change-Id: I4804239483f8b35bc3703aa62c2a8fd642e0234a
Original-Signed-off-by: philipchen <philipchen@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/433039
Original-Commit-Ready: Philip Chen <philipchen@chromium.org>
Original-Tested-by: Philip Chen <philipchen@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18296
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
It's an attempt to consolidate the access code, even if there are still
multiple implementations in the code.
Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18265
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since it checks for DDR3 style checksums, it's a more appropriate name.
Also make its configuration local for a future code move.
Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18264
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Also make sure that no board changes behaviour because of that by adding
a static assert.
TEST=abuild over all builds still succeeds (where it doesn't if
DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the
device/dram code).
Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18254
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Shorten field names of struct cbmem_console since saying "buffer_" in
front of everything is redundant and we can use the gained space to save
some line breaks in the code later. This also aligns the definition with
the version in libpayload.
Change-Id: I160ad1f39b719ac7e912d0466c82a58013cca0f9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18299
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.
Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18285
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The apollolake boards don't have an me.bin proper, but they still have
descriptor regions which need to be locked down. Therefore, remove the
restriction of HAVE_ME_BIN from LOCK_MANAGEMENT_ENGINE.
BUG=chrome-os-partner:62177
TEST=For apollolake one can select LOCK_MANAGEMENT_ENGINE.
Change-Id: I73aab3a604ec25cd56d760bf76cc21c5a298799e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18304
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Dump the CSE status registers for potential debugging purposes.
Explicitly call out manufacturing mode of the part since it's
important shipping devices ensure manufacturing mode is locked
down. Intel is planning on writing a common driver so a complete
status -> string dumps was not done because (surprise surprise)
not all the fields are equal with previous implementations.
BUG=chrome-os-partner:62177
BRANCH=reef
TEST=Booted and noted dump of CSE status registers.
Change-Id: I71d15722bb193877f1569c1d3e7f441302f5bd14
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18303
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This fixes an issue on systems where the S3 state in the pm1 control
registers are not cleared when vboot determines recovery mode is
required on an S3 resume. The EC code will reboot the system knowing
that the EC was in RW. However, on subsequent entry into romstage the
S3 path will be taken and fails to recover cbmem -- forcing another
reboot. To work around that, signal to the platform a reboot is
happening and let the platform perform the necessary fix ups to the
register state.
BUG=chrome-os-partner:62627
Change-Id: Ic144b11b4968c92a1273b8d9eb9dc10f0056bf3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18295
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Eve is a convertible add support for sending Tablet mode switch
changes from EC to AP.
Change-Id: I35133ebc1439852d0ceb88d7d679b37356b0869d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/18276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add a new driver GOOG0006 to report tablet switch
to user space.
On glados based convertible, check that with a new kernel driver
(cros_ec_tbmc) that evtest collects tablet switch changes.
Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430951
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/18173
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Options with no prompt can go anywhere in the tree with the same
dependencies and they have the same effect. Moving them lower in
the tree allows the default values to be overridden by other Kconfig
files.
This patch just moves options with default values that aren't 'n'. The
'n' options are just removed in the next patch, since they aren't needed.
Verified that this makes no significant changes to any config file.
Change-Id: I46175756b937a241edba87dbf70ce1be851fa89d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17907
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The WAK_STS bit is not set in a wake from G3, so the check for this
bit needs to only be done when checking for a wake from S3.
This change correctly enables the keyboard backlight in wake from G3
and only does not enable it during a wake from S3.
BUG=chrome-os-partner:58666
TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard
backlight turns on like it does when waking from S5. Also force enter
hibernate with Alt+VolumeUp+H and then power back up and ensure that
the keyboard backlight is enabled when booting.
Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18280
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For Kconfig options that we might want to override the default,
move the fallback default to the bottom of the file. This allows
the default to be set anywhere else, without requiring a select.
This is especially important for non-boolean symbols, which can't
have their defaults overridden in the Kconfig. Those can only be
updated in a saved config file.
Verified that this makes no significant changes to any config file.
Change-Id: I66034f356428f4ccd191d7420baf888edd5216dc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Given a specification of bitfields defined e.g. as follows:
specfile:
{
"field1" : 8,
"field2" : 4,
"field3" : 4
}
and a set of values for setting defaults:
setterfile:
{
"field1" = 0xff,
"field2" = 0xf,
"field3" = 0xf
}
You can generate a binary packed blob as follows:
./blobtool specfile setterfile binaryoutput
binaryoutput: ff ff
The reverse is also possible, i.e. you can regenerate the setter:
./blobtool -d specfile binaryoutput setterorig
setterorig:
# AUTOGENERATED SETTER BY BLOBTOOL
{
"field1" = 0xff,
"field2" = 0xf,
"field3" = 0xf
}
This tool comes with spec/set files for X200 flash descriptor
and ICH9M GbE region, and can be extended or used to decompile
other data blobs with known specs.
Change-Id: I744d6b421003feb4fc460133603af7e6bd80b1d6
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17445
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
When guado/rikku/tidus were rolled into jecht, an error was
made in set_power_led() as guado/rikku set the polarity
differently than tidus. Fix the power LED for guado/rikku
by setting the polarity correctly.
Test: boot guado/rikku and observe proper function of power LED
under S0, S3, and S5 power states.
Change-Id: I23072ac60bc9683776f748ca1326d98257c3c54f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18249
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Bit 16 in BLC_PWM_CTL enables brightness controls, but the
current value is generic. Use the proper value, obtained
by reading BLC_PWM_CTL while running the VBIOS.
Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: https://review.coreboot.org/10624
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reason for revert:
Pyro has two touchscreen sources: WACOM/ELAN.
It will not have both touchscreen IC in one system at the same time.
So the "probed" property of WACOM i2c device is mandatory to set for kernel
to know whether it exists before driver initializes it.
Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF
will be invoked to set GPIO#152 low to cut off power.
BUG=chrome-os-partner:62371
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This also selects RELOCATABLE_RAMSTAGE and
CACHE_RELOCATABLE_RAMSTAGE_OUTSIDE_CBMEM by default on Haswell.
Change-Id: I50b9ee8bbfb3611fccfd1cfde58c6c9f46b189ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18232
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change fixes the two sets of pins that were swapped in the
map of DQS signals from CPU to DRAM for channel 1.
Although this does not appear to have any impact to the system it
does result in different register values for DQS pin mapping that
are programmed inside FSP.
BUG=chrome-os-partner:58666
TEST=This fix was verified against the current schematic and using
FSP debug output.
Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18279
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The selection of the SSC reference frequency for LVDS was based on a
completely unrelated clock.
The `ssc_freq` flag should be set when the SSC reference runs at a
different frequency than the general display reference clock (DREF).
For most platforms, there is no choice, i.e. for i945 and gm45 the SSC
reference always differs from the display reference clock (i945: 66Mhz
SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and
newer, it's the same frequency for SSC/non-SSC (120MHz). The only,
currently supported platform with a choice seems to be Pineview, where
the alternative is 100MHz vs. the default 96MHz.
Change-Id: I7791754bd366c9fe6832c32eccef4657ba5f309b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
same change as I49935e659bf67225d3f5db1b06acc2cd046dcd74
this is required for poppy board as well.
GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals
when doing GPIO-driven I2S. This needs to be high by default so
the DSP can drive these signals, instead of low where it is enabled
for GPIO-driven I2S and the DSP cannot drive these signals.
BUG=None
BRANCH=None
TEST=play test sound in OS over internal speaker
Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18282
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals
when doing GPIO-driven I2S. This needs to be high by default so
the DSP can drive these signals, instead of low where it is enabled
for GPIO-driven I2S and the DSP cannot drive these signals.
BUG=chrome-os-partner:58666
TEST=play test sound in OS over internal speaker
Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18281
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The me_cleaner option is available on multiple platforms:
* Sandy and Ivy Bridge (well tested by multiple users).
* Skylake and Braswell (tested).
* Haswell, Broadwell and Bay Trail (untested).
The untested platforms have been included anyways because all the
firmwares are very similar and Intel ME/TXE probably behaves in the
same way.
Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18206
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add VFCT table to provide PCI Optiom Rom for
AMD graphic devices.
Useful for GNU Linux payloads and embedded dual GPU systems.
Tested on Lenovo T500 with AMD RV635 as secondary gpu.
Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Reviewed-on: https://review.coreboot.org/18192
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Sooi, Li Cheng