Commit graph

8 commits

Author SHA1 Message Date
Gaggery Tsai
c14307e50a soc/intel/skl: Add AML IccMax and remove unused info
This patch adds AML IccMax for VR configuration. From doc #594883, the
IccMax for Core was changed to 28A, we need this patch to accommodate
the changes. Besides, removes unused sku information from
sku_icc_max_mapping structure.

BUG=b:110890675
BRANCH=None
TEST=Remove icc_max from DT &
     emerge-atlas coreboot chromeos-bootimage &
     Tested with AML-Y and KBL-Y SKUs.

Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27610
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06 07:58:06 +00:00
Elyes HAOUAS
143fb46d47 soc/intel/skylake: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: Idf00c029331aba30c8bfca71546cad62ff6bb0a7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26541
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04 02:35:42 +00:00
Patrick Rudolph
e56189cfd1 pci: Move inline PCI functions to pci_ops.h
Move inline function where they belong to. Fixes compilation
on non x86 platforms.

Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20 13:03:54 +00:00
Gaggery Tsai
e1a75d4a94 soc/intel/skylake: Override KBL IccMax settings
According to Intel document #559100 KBL EDS v2.8, section 7.2
DC specifications, the IccMax setting for KBL-U, KBL-U42 and
Celeron/Pentium are different. This patch overrides the IccMax
settings for KBL-U/R/Y since device tree could not handle all
KBL-U/R combinations when multiple SKUs are adopted in a project.
Besides, it is inefficient to maintain the same code for all
variants. Hence, place it in the common code so that all variants
could leverage the benefits.

+----------------+-------------+---------------+------+-----+
| Domain/Setting |  SA         |  IA           | GTUS | GTS |
+----------------+-------------+---------------+------+-----+
| IccMax(KBL-U/R)| 6A(U42)     | 64A(U42)      | 31A  | 31A |
|                | 4.5A(Others)| 29A(Celeron)  |      |     |
|                |             | 32A(i3/i5)    |      |     |
+----------------+-------------+---------------+------+-----+
| IccMax(KBL-Y)  | 4.1A        | 24A           | 24A  | 24A |
+----------------+-------------+---------------+------+-----+

BUG=b:71369428
BRANCH=None
TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot
     chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron
     SKUs are identified correctly and IccMax settings are passed
     to FSPS correctly.

Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12 18:21:15 +00:00
Duncan Laurie
86db469871 intel/skylake: Support for setting AC/DC loadline
Add options to set the AC and DC loadline values for each supported
VR type so these can be tuned on a per-board basis in devicetree.cb.

BUG=b:36228330
BRANCH=none
TEST=Build and boot on Eve and check debug FSP output to ensure that
it is applying the provided loadline values

Change-Id: I2a5533d2c9fd86351c86584e3738e80ac4c1f915
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18819
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-15 19:45:55 +01:00
Duncan Laurie
4fa8a6f4fe intel/skylake: Fix bug in VR configuration with FSP 2.0
With the move to FSP 2.0 the number of VR types supported was
reduced to 4, and the VR_RING type is no longer present.

This means all existing boards using FSP 2.0 are incorrectly
passing VR configuration into FSP as the values corresponding to
"GT Sliced" and "GT Unsliced" have changed.

Fix this by updating the skylake SOC VR handling to account for
changes in the FSP configuration and no longer provide VR_RING
type when using FSP 2.0.

BUG=b:36228330
BRANCH=none
TEST=manual: build and boot on Eve

Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2017-03-15 19:45:42 +01:00
Rizwan Qureshi
1222a73205 skylake: Add initial FSP2.0 support
Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.

The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.

Add the below files,
car_stage.S:
	Add romstage entry point (car_stage_entry).
	This calls into romstage_fsp20.c and aslo handles
	the car teardown.
romstage_fsp20.c:
	Call fsp_memory_init() and also has the callback
	for filling memory init parameters.

Also add monotonic_timer.c to verstage.

With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.

TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0

Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-31 20:02:07 +02:00
Aaron Durbin
df21440d68 intel/skylake: provide default VR configuration
FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is
non-zero. That behavior is not desired because it's not clear what
the behavior will be for various processor SKUs. Instead provide
default values for the VR config. Note that PSI3 and PSI4 are not
enabled for those defaults.

BUG=chrome-os-partner:48466
BRANCH=None
TEST=Built and booted glados.

Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17
Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318263
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12983
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:12:12 +01:00