Commit Graph

4753 Commits

Author SHA1 Message Date
Elyes Haouas 898176a24c treewide: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 18:00:16 +00:00
Elyes Haouas 7d67a19cfa util/amdfwtool/amdfwtool: Don't rewrite macros
Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 17:59:20 +00:00
Arthur Heymans a83c502d5a util/amdfwtool: Add more instances some types in BDT
Some hardware uses more instances.

Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 00:41:54 +00:00
Arthur Heymans 1f05c8044e util/amdfwtool: Add new types
These are used on newer platforms.

Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-11-11 00:40:22 +00:00
Kacper Stojek 76d2b6699d util/inteltool: Add support for Elkhart lake
Document: 614109, 601458
Tested on: Protectli vault_ehl (VP2420)

Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Change-Id: I54948741082ca1072642046f64539a4c15ddb578
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-11-10 16:24:49 +00:00
Martin Roth 815c3634e3 util/scripts: Add script to run abuild on specific SOCs
This finds all the boards using a specified Kconfig option and runs both
CrOS and non-CrOS abuilds on them to make sure they're working.

Nobody wants to run the full what-jenkins-does build on their host
machine.  Hopefully this can help get some tests run locally before
pushing to coreboot.org.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-10 00:19:55 +00:00
Shaik Shahina 425413c35f cbfstool: Fix possible memory leak
Handle the possible memory leak scenario.

Foundby=klocwork
BUG=NONE
TEST=Boot to OS on Nivviks

Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69220
Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-09 00:26:30 +00:00
Solomon Alan-Dei a2503fa2e9 util/cbfstool/bpdt_formats: Fix memory leak issues
The functions create_bpdt_hdr and create_cse_layout
in bpdt_1_6.c are defined to return pointers but
not integers as was previouly implemented.

Reported-by: Coverity(CID:1469323)
Reported-by: Coverity(CID:1469353)

Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: Idb78d94be7a75a25ad954f062e9e52b1f0b921dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-08 22:51:36 +00:00
Ravi Mistry d92745bb98 util/superiotool/fintek.c: Fix F71808A hardware monitor readouts
Fix readouts from the hardware monitor on Fintek F71808A Super I/O.
The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61.

Referred to util/superiotool/winbond.c and the Linux kernel driver f71882fg.

Tested on a HP 500-319na (Memphis-S / IPM87-MP).

Signed-off-by: Ravi Mistry <rvstry@protonmail.com>
Change-Id: I2b2b98c62f9305c6f4885c2ce3b1444801dcb9d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 23:20:08 +00:00
Martin Roth 65a0e5a92d util/scripts: Add script to show platforms, CPU, type, and date added
This is the script used to generate the list of platforms that were
removed from the master branch at each release.  Generate a list for the
old branch, another for the new, and compare the two.

Representative output:
```eval_rst
+-------------------------+-------------------+------------+----------+
| Vendor/Board            | Processor         | Date added | Brd type |
+=========================+===================+============+==========+
| 51nb/x210               | INTEL_KABYLAKE    | 2020-03-16 | laptop   |
| acer/aspire_vn7_572g    | INTEL_SKYLAKE     | 2022-01-28 | laptop   |
| acer/g43t-am3           | INTEL_X4X         | 2020-09-28 | desktop  |
| amd/bilby               | AMD_PICASSO       | 2021-02-17 | eval     |
| amd/birman              | AMD_MORGANA       | 2022-10-10 | eval     |
| system76/whl-u          | INTEL_WHISKEYLAKE | 2021-04-14 | laptop   |
| ti/beaglebone           | TI_AM335X         | 2013-05-26 | sbc      |
| up/squared              | INTEL_APOLLOLAKE  | 2019-05-22 | mini     |
+-------------------------+-------------------+------------+----------+
```

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4f7265d95df31f3a74aa2aa164f6a094c1139750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 14:16:47 +00:00
Martin Roth 90e4f3dd4c util/cbmem: Update formatting for cbmem -l command
Some of the cbmem area names have gotten longer, and were making the
output of cbmem -l look bad, so expand the name area to 20 characters.

Instead of printing a blank area if the name isn't recognized, call it
unknown.

Change the method of printing the title to match the way the actual text
of the table is printed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04 01:07:37 +00:00
Michael Niewöhner 8cfd3f88d3 checkpatch: add Co-authored-by to signature list
Co-authored-by is commonly used for changes that have more than one
author. Add it to the list to make Jenkins happy.

Change-Id: I7f66824febe3be756c64ebf44c94bc653a66f1e1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-11-04 00:36:11 +00:00
Patrick Georgi 3d0303a57c util/docker/coreboot.org-status: Rewrite parser
The current tool is a shell script that mixes data collection and HTML
generation and is generally a pain to work with. It takes 15 minutes to
run.

The new tool is written in go, collects all data first, then generates
the output HTML from the data and a single template, and finishes in
10 seconds.

The goal in this version is to produce output as similar as possible to
the output of the shell script. Some difference will remain because the
shell script returns some trash data whose reproduction would require
more effort than is worth.

Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2022-11-03 13:50:30 +00:00
Hsuan Ting Chen 5faaca09b8 util/eventlog: Correct the capitalization for diagnostics types
Correct the capitalization of ELOG_CROS_DIAG_TYPE_STORAGE_HEALTH from
"Storage Health Info" to "Storage health info", which is already widely
used in depthcharge diagnostics tools.

BUG=b:254405481
TEST=none

Change-Id: Ia6c1df9e8d2ee6f8ae11b962e76b52f3c6663c42
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-02 21:41:10 +00:00
Solomon Alan-Dei b4e94c8b01 util/cbfstool: fix memory leak in compress.c
free the memory allocated in lz4_compress
function before returning from it.

Reported-by: Coverity (CID:1469433)

Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: I8698090d519964348e51fc3b6f2023d06d81fcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-02 21:40:25 +00:00
Martin Roth b621d9bef3 util/release/build-release: Use bash arrays for params
Instead of using unquoted strings for the command line parameters,
use arrays which naturally split into separate elements inside the
quotes.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1c96d5072b98523af4e407cfff8f4d1d28ec3297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-02 20:51:47 +00:00
Patrick Georgi aa8796d3fd util/kconfig: Uprev to Linux 6.0's kconfig
Only minor changes in kconfig this time that shouldn't
affect us.

TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same

Change-Id: I77cc8517128a973c345c41da2c483b78eeaee89f
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:47:21 +00:00
Patrick Georgi 1215cc7632 util/kconfig: Uprev to Linux 5.19's kconfig
Only minor changes in kconfig this time that shouldn't
affect us.

TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same

Change-Id: Icc83c929dd1ea2d98e1a789560ce26886ded1f12
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:46:50 +00:00
Patrick Georgi 5526be21ea util/kconfig: Uprev to Linux 5.18's kconfig
Only minor changes in kconfig this time that shouldn't affect us.

TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same

Change-Id: I46f43182ce9ec1b6a5923cb77dcd6e335e44c87a
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:46:23 +00:00
Patrick Georgi 7eb03cb657 util/kconfig: Uprev to Linux 5.17's kconfig
Another upstream refactoring, another local patch gone!

TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same

Change-Id: I0f99dcbd8ecc7256551f0a6e2c83c060cb1999b6
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:46:03 +00:00
Patrick Georgi 4c9b9e9709 util/kconfig: Uprev to Linux 5.16's kconfig
Linux 5.16 saw a significant rewrite in the boolean handling which
reduces our change set. On the other hand, it's all new code.

Comparing the config.build and config.h files generated by
`util/abuild/abuild -C`, only a few lines of comment in the header
changed.

Change-Id: I52984e15a48236ddf228707aec85e90f71aa4382
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:45:52 +00:00
Solomon Alan-Dei a6e60f043b util/lint: fall back to regular grep in kconfig_lint
Automatically fall back to using regular grep if working outside a git
repository and the option to use regular grep is not specified

Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: I0cdecf01a0e74c30947c4fe7e7c7d9457a5165a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-29 15:43:18 +00:00
Matt DeVillier 0923c62448 util/chromeos/extract_blobs: try using RW_MAIN_A region first
Since the RW firmware may contain newer/additional blobs than the
RO COREBOOT region, try using it first, then fall back to
COREBOOT and eventually BOOT_STUB if necessary.

TEST=extract blobs from dedede and brya firmware images

Change-Id: Ia01b37f8c410685de8a17ea4105ca671931a47c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-29 02:39:39 +00:00
Michael Niewöhner 8eb7b35010 lint/checkpatch: consider leading + in the line length limit check
The line length limit in coreboot's coding style guidelines applies to
the final file, while checkpatch currently checks the patch line length.
Since patches´ lines start with a `+` (only added content is checked),
the line length being checked is one character longer than the actual
content.

Increase max_line_length by 1 to take this into account.

Change-Id: I8da45bb0d5fbe7d0e12c8b181cf01e5685186bf6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-28 15:57:06 +00:00
Karthikeyan Ramasubramanian da5d0251f5 util/cbfstool: Check for metadata hash in verstage
Metadata Hash is usually present inside the first segment of BIOS. On
board where vboot starts in bootblock, it is present in bootblock. On
boards where vboot starts before bootblock, it is present in file
containing verstage. Update cbfstool to check for metadata hash in file
containing verstage besides bootblock.

Add a new CBFS file type for the concerned file and exclude it from CBFS
verification.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 and PSP verstages.

Change-Id: Ib4dfba6a9cdbda0ef367b812f671c90e5f90caf8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66942
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:59:58 +00:00
Karthikeyan Ramasubramanian 7835861f9d util/amdfwtool: Add build rules for amdfwread
Add build rules to build amdfwread tool. Also mark this as a dependency
either while building tools or amdfw.rom.

BUG=None
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:37 +00:00
Karthikeyan Ramasubramanian 8b86f21f45 util/amdfwtool/amdfwread: List AMDFW RO binary entries
Add support to walk through PSP L1, PSP L2, BIOS L1, BIOS L2 directories
and list the entries present in them. Accommodate both recovery A/B
layout and normal layout. This is required to identify the location and
size of each entries in the finally built amdfw.rom. This in turn can be
used to perform any platform specific verification on the relevant
components.

BUG=None
TEST=Build and list the contents of AMDFW binary.
/usr/bin/amdfwread --ro-list /build/skyrim/firmware/image-skyrim.bin
Table: FW   Offset     Size
PSPL1: Dir  0x00d97000
+-->PSPL1: 0x48 0x00d98000 0x00001000
    +-->PSPL2: Dir  0x00c30000
        +-->PSPL2: 0x00 0x00c31000 0x00000440
        +-->PSPL2: 0x01 0x00c31500 0x00007580
        +-->PSPL2: 0x02 0x00c38b00 0x00019470
        +-->PSPL2: 0x08 0x00c52000 0x0001f560
        +-->PSPL2: 0x09 0x00c71600 0x00000440
        +-->PSPL2: 0x0b 0x430000041(Soft-fuse)
        +-->PSPL2: 0x0c 0x00c71b00 0x00023100
        +-->PSPL2: 0x12 0x00c94c00 0x00015890
        +-->PSPL2: 0x13 0x00caa500 0x000021c0
        +-->PSPL2: 0x20 0x00cac700 0x00000640
        +-->PSPL2: 0x21 0x00cace00 0x00000030
        +-->PSPL2: 0x22 0x00cad000 0x00001000
        +-->PSPL2: 0x24 0x00cae000 0x00003b60
        +-->PSPL2: 0x28 0x00cb1c00 0x00022890
        +-->PSPL2: 0x2d 0x00cd4500 0x00003100
        +-->PSPL2: 0x30 0x00cd7600 0x0006b550
        +-->PSPL2: 0x3a 0x00d42c00 0x000006d0
        +-->PSPL2: 0x3c 0x00d43300 0x000018c0
        +-->PSPL2: 0x44 0x00d44c00 0x00006610
        +-->PSPL2: 0x45 0x00d4b300 0x00001c70
        +-->PSPL2: 0x50 0x00d4d000 0x00001a00
        +-->PSPL2: 0x51 0x00d4ea00 0x00001020
        +-->PSPL2: 0x52 0x00d4fb00 0x00010180
        +-->PSPL2: 0x55 0x00d5fd00 0x00000600
        +-->PSPL2: 0x5a 0x00d60300 0x00000570
        +-->PSPL2: 0x5c 0x00d60900 0x00000b20
        +-->PSPL2: 0x71 0x00d61500 0x00024710
        +-->PSPL2: 0x73 0x00d85d00 0x00010640
        +-->PSPL2: 0x8d 0x00d96400 0x00000030
        +-->PSPL2: 0x49 0x00d99000 0x00001000
            +-->BIOSL2: Dir  0x00d99000
                +-->BIOSL2: 0x60 0x00d9a000 0x00009924
                +-->BIOSL2: 0x68 0x00da4000 0x00009924
                +-->BIOSL2: 0x61 0x2001000(DRAM-Address)
                +-->BIOSL2: 0x62 0x00dada00 0x00010000
                +-->BIOSL2: 0x63 0x00000000 0x0001e000
                +-->BIOSL2: 0x64 0x00db4200 0x00006310
                +-->BIOSL2: 0x65 0x00dba600 0x000004e0
                +-->BIOSL2: 0x64 0x00dbab00 0x00006180
                +-->BIOSL2: 0x65 0x00dc0d00 0x00000250
                +-->BIOSL2: 0x6b 0x201f000(DRAM-Address)
+-->PSPL1: 0x4a 0x00d98000 0x00001000

Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66761
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:18 +00:00
Karthikeyan Ramasubramanian 0b6e63220f util/amdfwtool/amdfwread: Handle recovery A/B layout
Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to
handle it.

Also add a generic read_header function to read different header types.

BUG=None
TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to
dump the Softfuse entry.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:04 +00:00
Karthikeyan Ramasubramanian 45257abb79 util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask
Optional arguments that involve printing information from the firmware
image is mapped to bit fields with bit 31 set. But instead of just
setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66573
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:55:53 +00:00
Karthikeyan Ramasubramanian 852c5dc101 util/amdfwtool/amdfwread: Update relative_offset function
* AMD_ADDR_PHYSICAL refers to physical address in the memory map
* AMD_ADDR_REL_BIOS is relative to the start of the BIOS image
* AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS
tables

Update the relative_offset implementation accordingly. Though
AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify
the relative_offset implementation so that it can be used for both PSP
and BIOS firmware tables. Hence update the relative_offset function
signature as well.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 15:55:22 +00:00
Michał Żygowski b205c5d8c1 util/superiotool/nuvoton.c: fix NCT6687D PP LDN typo
Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the
patch adding register definitions for NCT6687D Super I/O chip.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-24 09:08:40 +00:00
Elyes Haouas 1e336dd91e scripts/update_submodules: Fix "bad revision" error
Fix "bad revision" error when we run "update_submodules" with no option.
This adds "origin/trunk" branch name for "util/goswid".

Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-23 02:39:27 +00:00
Arthur Heymans 1cffc55d35 util/amdfwutil: Fix adding microcode binaries
Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 21:40:08 +00:00
Martin Roth 95b5b025a0 util/lint: Fix linting outside of git repos
If the coreboot code is not in a git repository, the linters switch
from using `git ls-files` to find.  This requires some changes to
prevent the linters from looking at the wrong files which are
automatically excluded by git.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I81d138760c29a7c476280bb9d963f6be99c75d6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:30:42 +00:00
Hsuan Ting Chen fec16a3574 util/elogtool: Add support for parsing CrOS diagnostics log
Remove the "_DEPRECATED_" tag from ChromeOS diagnostics event and add a
subtype: "ELOG_CROS_DIAGNOSTICS_LOGS" under it.

The data of "ELOG_CROS_DIAGNOSTICS_LOGS" (0x02) contains:
* An uint8_t of subtype code
* Any number of "ChromeOS diagnostics logs" events

Each "ChromeOS diagnostics log" represents the result of one ChromeOS
diagnostics test run. It is stored within an uint8_t raw[3]:
 * [23:19] = ELOG_CROS_DIAG_TYPE_*
 * [18:16] = ELOG_CROS_DIAG_RESULT_*
 * [15:0]  = Running time in seconds

Also add support for parsing this event. The parser will first calculate
the number of runs it contains, and try to parse the result one by one.

BUG=b:226551117
TEST=Build and boot google/tomato to OS,
localhost ~ # elogtool list
0 | 2022-09-26 04:25:32 | Log area cleared | 186
1 | 2022-09-26 04:25:50 | System boot | 0
2 | 2022-09-26 04:25:50 | Firmware vboot info | boot_mode=Manual recovery
  | recovery_reason=0x2/0 (Recovery button pressed)
  | fw_tried=A | fw_try_count=0 | fw_prev_tried=A
  | fw_prev_result=Unknown
3 | 2022-09-26 04:25:50 | EC Event | Keyboard Recovery
4 | 2022-09-26 04:26:01 | Memory Cache Update | Normal | Success
5 | 2022-09-26 04:26:06 | System boot | 0
6 | 2022-09-26 04:26:07 | Firmware vboot info | boot_mode=Diagnostic
  | fw_tried=A | fw_try_count=0 | fw_prev_tried=A
  | fw_prev_result=Unknown
7 | 2022-09-26 04:26:07 | Diagnostics Mode | Diagnostics Logs
  | type=Memory check (quick), result=Aborted, time=0m0s
  | type=Memory check (full), result=Aborted, time=0m0s
  | type=Storage self-test (extended), result=Aborted, time=0m1s

Change-Id: I02428cd21be2ed797eb7aab45f1ef1d782a9c047
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-14 16:06:39 +00:00
Fred Reitberger 9049dfdb68 util/cbfstool: Wrap logging macros in do - while
Wrap the console logging macros with do { ... } while (0) so they act
more like functions.

Add missing semicolons to calls of these macros.

TEST=compile only

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I721a4a93636201fa2394ec62cbe4e743cd3ad9d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-13 17:07:02 +00:00
Michał Żygowski b33ee1da7d util/superiotool/nuvoton.c: Add NCT6687D-W register definitions
Based on public NCT6686D hardware datasheet revision 0.5 which should
be similar to NCT6687D.

TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-12 09:07:21 +00:00
Arthur Heymans ee0f5d794d util/amdfwread: Fix cookie error message
Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-11 14:45:09 +00:00
Arthur Heymans aafbe136a9 util/amdfwutil: Order enum and use hex consistently
This makes it easier to match the code to the datasheet (55758, NDA
only).

This also removes the duplicate lines:
"{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH |
PSP_LVL2_AB },
{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH |
PSP_LVL2_AB },"

TESTED: google/vilboz still boots.

Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-10-11 14:44:31 +00:00
Fred Reitberger 7e9801171e util/amdfwtool: Add Mendocino to usage
Add missing Mendocino soc to usage print.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:50:44 +00:00
Martin Roth 134908381f util/amdfwtool: Add preliminary code for morgana & glinda SOCs
This allows amdfwtool to recognize the names for the upcoming morgana
and glinda SoCs.  It does not yet do anything for those SoCs, but this
allows the morgana SoC to build.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:45:07 +00:00
Fred Reitberger 743c1c0894 util/lint/lint-stable-003-whitespace: Fix shell variable name
Fix shell variable "LINTDIR" so that helper_functions.sh can be found.

TEST=`./util/lint/lint lint-stable --junit` no longer prints "cannot
open /helper_functions.sh: No such file"

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I68f2e65fa1c9297ad6b58b77576deaeef8bd76e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-10 21:43:47 +00:00
Angel Pons f007ab7b43 util/inteltool: Add support for (non-ULT) Broadwell
Add support for traditional (non-ULT) Broadwell.

Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08 21:04:43 +00:00
Angel Pons aa4cd73409 util/inteltool: Add 9 series PCH support
Add the PCI device IDs for 9 series PCHs.

Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08 21:03:58 +00:00
Sean Rhodes 3c3516b874 util/coreboot-configurator: Update the README
Update the README with new instructions for Debian 11 and MX Linux.

Also add the build dependencies.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-07 22:06:06 +00:00
Kacper Stojek fb9110b9e4 util/inteltool: Add support for Alderlake P in inteltool
TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P

Document number: 626817, 630094, 655258

Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 21:18:22 +00:00
Kangheui Won 5b84dfd1c1 util/amdfwtool: Generate hashes for signed AMDFW components
Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage
can pass it to PSP. The PSP will use these hashes to verify the
integrity of those signed firmwares.

BUG=b:203597980
TEST=Build Skyrim BIOS image.

Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:13:38 +00:00
Kangheui Won 3c164e13e7 util/amdfwtool: Add options to separate signed firmwares
Add support for separating signed firmwares into another CBFS. If
sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware
is signed against AMD chain of trust and will be verified by PSP. If
those firmware binaries are put outside FW_MAIN_[AB], vboot can skip
redundant verification, improving overall verification time.

BUG=b:206909680
TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS.

Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:11:13 +00:00
Karthikeyan Ramasubramanian 236245ec7d util/amdfwtool: Include the header with __packed definition
Checkpatch script recommends to use __packed instead of
__attribute__((packed)). Currently the build rule for amdfwtool does not
include the required header file with __packed definition. Update the
compiler flag to include the required header file.

BUG=None
TEST=Build amdfwtool.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:09:01 +00:00
Tom Hiller 520c8c070b util/docker/coreboot-sdk: add graphicsmagick-imagemagick-compat
edkII requires ImageMagick's `convert` to compile.  The
`graphicsmagick-imagemagick-compat` package provides `convert` without
the full ImageMagick library.

Change-Id: I8fc01526842eb408b0015c0652043c20f826a015
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-10-02 22:07:56 +00:00
Martin Roth d81debd946 util/lint: Update tools that use git to use a library
Each of the tools that used git had similar functionality. This combines
all of that into a single script that gets sourced by each.  This makes
maintenance much easier.

By doing this and updating each of the scripts to do the correct thing
if the script isn't being run in a git repository, it makes them work
much better for the releases, which are just released as a tarball,
without any attached git repository.

Change-Id: I61ba1cc4f7205e0d4baf993588bbc774120405cb
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 19:19:53 +00:00
Martin Roth 7726a7f272 util/lint: Update spelling.txt, add makefile to sort it
- Update spelling.txt with Lintian changes
- Remove words that are going to mess up code
- Add comments to the header about what words should be removed, along
with where the files
- Add Makefile to sort the list

Note that this undoes some of the sorting that Patrick introduced in
commit CB:38632 - ID: 805b291830
I just cannot reproduce his sort order, even using the script he put
into the commit message.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic131d5b08409f43eb700dcc8f125af00cff53d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64893
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 19:07:02 +00:00
Felix Held 3dfb485334 util/amdfwtool/data_parse: fix PMU subprogram/instance ID handling
The parsing of the PMU binary subprogram and instance numbers only
worked correctly for the cases where the ID in the name in the fw.cfg
file was between 0 and 9, but returned wrong results if it was between a
and f. Switch to using strtol with a base of 16 instead of subtracting
the char '0' from the char in the filename in
find_register_fw_filename_bios_dir to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-30 18:03:50 +00:00
Robert Zieba de6ecd0101 util/spd_tools: Change Mendocino to use 0x13 for LP5x memory type
Mendocino supports LP5x but currently doesn't support SPDs that use the
LP5x memory type, 0x15. This commit updates set 1 SPDs, which are
currently only used for mendocino, to use 0x13 for their memory type.

BUG=b:245509394
TEST=Generated SPDs, verified that only set 1 have changed to 0x13

Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-29 17:12:00 +00:00
Denis 'GNUtoo' Carikli b82486496d intelmetool: Add PCI ID for Bay Trail
Tested on a Dell Venue 8 Pro tablet

Change-Id: Ic8f162ea82b910082af4b4e05fa1408fd24f2c88
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-28 18:22:27 +00:00
Ritul Guru a2cb3400a6 util/amdfwtool: Add support for PSP NVRAM base addr and size
Add parameters to support adding the location and size of
the PSP NVRAM area to the PSP directory table.

Verified this change on PCO based Bilby platform.
Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 17:10:46 +00:00
Sean Rhodes 3c43301185 util/coreboot-configurator: Update legacy_8254_timer description
The help text and label for legacy_8254_timer is inverted, so update
this so that it is correct.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I866a15886d1cfd2b77094742787dee7a36a54e85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65348
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 15:13:22 +00:00
Sean Rhodes 914f50552f util/coreboot-configurator: Add RPM spec file
Add RPM spec to allow building RPMs, for both coreboot-configurator
and nvramtool, for Fedora.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I80a77d0f2246409c06e22abb229d63c4611a9fb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65346
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 15:13:07 +00:00
Sean Rhodes ed0c7f53eb util/coreboot-configurator: Update Debian dependancies
Change the control file to allow either libyaml-cpp0.6 or
libyaml-cpp0.7.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I754d3e2018ab78fcb657d313c8662313738b190a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-22 15:12:59 +00:00
Jakub Czapiga a0e36d8cba tests: Add support for tests build failures detection
This patch introduces new target: junit.xml-unit-tests, which builds and
runs unit-tests. It also creates build log containing build logs. This
feature allows for one to see build failures in Jenkins dashboard.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I94184379dcc2ac10f1a47f4a9d205cacbeb640fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67372
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-21 14:06:42 +00:00
Elyes Haouas c8870b1334 crossgcc: Upgrade llvm from version 14.0.6 to 15.0.0
Test build for QEMU x86 i440fx/piix4.

Change-Id: I3144a83fcbd92eec51d70e9be33ff2fcb2821731
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67416
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18 17:14:10 +00:00
Elyes Haouas 035e9f9f0c crossgcc: Upgrade cmake from 3.23.2 to 3.24.2
Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-18 17:14:04 +00:00
Yidi Lin 0811a6492d cbmem: use aligned_memcpy for reading lb_cbmem_entry information
The lbtable contains the memory entries that have fields unnaturally
aligned in memory. Therefore, we need to perform an aligned_memcpy() to
fix the issues with platforms that don't allow unaligned accesses.

BUG=b:246887035
TEST=cbmem -l; cbmem -r ${CBMEM ID}

Change-Id: Id94e3d65118083a081fc060a6938836f6176ab54
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-18 03:24:16 +00:00
Patrick Georgi f0d5f67e46 riscv: Enable the newfangled way of selecting instruction sets
gcc12+ will require riscv architecture selection to come not only with
featurei suffixd charactersa, it also comes with feature_ful suffix_ed
words_mith. Much creative, very appreciate.

To accommodate for this madness, enable the already existing (but off by
default) support for that in our gcc11 build, support using by detecting
the compiler's behavior in xcompile and pass that knowledge along to our
build system.

Then cross our fingers and hope for the best!

Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-17 05:56:34 +00:00
Elyes Haouas 3541c31add util/kconfig/regex.c: Remove leftover
coreboot doesn't support the MIPS architecture anymore.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I404d034949a7786d7971117081537baf27ff2e22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-16 14:52:44 +00:00
Elyes Haouas a3c287d7a3 crossgcc [binutils]: Remove 'enable-plugins' option
unneeded 'enable-plugins' option sneaked in..., so remove it.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id1d7f2c7e6b70c28e1060c6ee915363ffe412ef6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 13:06:22 +00:00
Elyes Haouas b8e5baf2f2 crossgcc [binutils]: Remove invalid enable-interwork option
'enable-interwork' is not a binutils configure option.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I29cd6137c700ff6871868a723daf33909aa218ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65609
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 13:05:44 +00:00
Nico Huber c0fc38eed8 sconfig: Allow to specify device operations
Currently we only have runtime mechanisms to assign device operations to
a node in our devicetree (with one exception: the root device). The most
common method is to map PCI IDs to the device operations with a `struct
pci_driver`. Another accustomed way is to let a chip driver assign them.

For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
ID lists grew very large and are incredibly error-prone. Often, IDs are
missing and sometimes IDs are added almost mechanically without checking
the code for compatibility. Maintaining these lists in a central place
also reduces flexibility.

Now, for onboard devices it is actually unnecessary to assign the device
operations at runtime. We already know exactly what operations should be
assigned. And since we are using chipset devicetrees, we have a perfect
place to put that information.

This patch adds a simple mechanism to `sconfig`. It allows us to speci-
fy operations per device, e.g.

  device pci 00.0 alias system_agent on
          ops system_agent_ops
  end

The operations are given as a C identifier. In this example, we simply
assume that a global `struct device_operations system_agent_ops` exists.

Change-Id: I2833d2f2450fde3206c33393f58b86fd4280b566
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15 13:06:47 +00:00
Jeremy Compostella e1465e2157 util/ifittool: Error out if microcodes do not fit the FIT table
parse_microcode_blob() returns success when it reaches max_fit_entries
microcode. It makes the FIT table size verification in
fit_add_microcode_file() useless. This patch makes
parse_microcode_blob() error out if max_fit_entries is reached.

Note that this size verification is critical as a FIT table only
partially listing the microcode patches can lead to boot failures as
recently observed on Raptor Lake-P.

BRANCH=firmware-brya-14505.B
BUG=b:245380705
TEST=compilation errors out when trying to stitch more than
     CONFIG_CPU_INTEL_NUM_FIT_ENTRIES microcode patches.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67454
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
2022-09-15 13:01:42 +00:00
Matt DeVillier 275a9a3d7e util/lint: Add a check for touchpads using the "probed" flag
As of commit 2cf52d80a6 ("mb/*/{device,override}tree: Set touchpads to
use detect (vs probed) flag") all touchpads in the tree have been
switched from using the 'probed' flag to 'detect.' Add a lint check to
ensure no touchpads are added with the probed flag.

TEST=manually change one touchpad to use 'probed' flag and ensure lint
check catches it.

Change-Id: Ie0aee2e3778fc56c6c21c97995738a147a1fa0d4
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67486
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14 20:52:02 +00:00
Elyes Haouas 8de4d27810 crossgcc: binutils: Remove invalid enable-multilibs option
Looks like somewhere after the original implementation it was renamed to
--enable-multilib without the s.
'enable-multilibs' is not a valid option for binutils.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I105cc9fa489aed24905dedb785c70bc69ed18970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65608
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-14 17:13:02 +00:00
Maxim Polyakov 593b0f1f23 intelp2m: Add Go Managing Dependencies System support
Add go.mod containing the full name of the project according to the
docs [1]: review.coreboot.org/coreboot.git/util/intelp2m, and also,
based on this, rename the internal packages to point to the absolute
path. This will allow Go Managing Dependencies System to integrate
packages from intelp2m to third-party Go written on the Go language [1].
This also requires fixing the Golang compiler version in go.mod: use
go1.18 [2], the latest up-to-date version.

[1] https://web.archive.org/web/20220910100342/https://go.dev/doc/modules/managing-dependencies
[2] https://web.archive.org/web/20220910100206/https://tip.golang.org/doc/go1.18

[ TEST ]
1) Import the coreboot project into some go project:

$cd path/to/go-project
$go get review.coreboot.org/coreboot.git
go: downloading review.coreboot.org/coreboot.git v0.0.0-20220903004133
-39914a50ae16
go: added review.coreboot.org/coreboot.git v0.0.0-20220903004133
-39914a50ae16

Thus, 'go get' correctly downloaded the contents of the repository.

2) Import intelp2m:

$cd path/to/go-project
$go get review.coreboot.org/coreboot.git/util/intelp2m
review.coreboot.org/coreboot.git/util/intelp2m imports
	./config: "./config" is relative, but relative import paths are
not supported in module mode
review.coreboot.org/coreboot.git/util/intelp2m imports
	./parser: "./parser" is relative, but relative import paths are
not supported in module mode

Thus, the problem is in the package names, but after this patch, the
import should be without errors.

3) Import a repository with an incorrect url:

$cd path/to/go-project
$go get review.coreboot.org/coreboot/test
go: unrecognized import path "review.coreboot.org/coreboot/test":
reading https://review.coreboot.org/coreboot/test?go-get=1:
404 Not Found

This has not happened in previous cases.

Change-Id: I12efae31227129b8c884af10fb233f398c4094e7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-09-12 12:55:05 +00:00
Jeremy Compostella 46ffccd753 util/ifittool: Fix buffer overflow with padded microcode patches
Some microcode patches are padded with zeros, which make
parse_microcode_blob() read beyond the end of the buffer.

BRANCH=firmware-brya-14505.B
BUG=b:245380705
TEST=No segmentation fault with a padded microcode patch

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67460
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-12 12:33:36 +00:00
Martin Roth 38bbff47a7 util/lint/lint: Add -I option to invert test results
To test the linters, we want to invert the results so that any test that
passes shows up as a failure. This will allow us to verify that all of
the linters are working correctly.

This will be tested nightly as well as on changes to the lint tools.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-07 22:35:02 +00:00
Caveh Jalali c762e231da util/spd_tools: Update LP5X support for ADL/RPL/MTL
This updates the SPD utility and generated SPDs for LP5X to use memory
type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on
Intel Tech Advisory Doc ID #616599 dated May 2022, page 15.

SPDs were regenerated with:
  "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5"

This only affects the SPDs for 2 memory parts for Intel SoCs and the
only board referencing these is rex.

BUG=b:242765117
TEST=inspected SPD hex dump

Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07 22:19:21 +00:00
Elyes Haouas 0d42db666b lint/checkpatch: Fix incorrect camelcase detection on numeric constant
This reduce the difference with linux v6.0-rc3.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I15e1a935665c38b8a2109d412b1d16f935cbb402
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-06 17:59:55 +00:00
Martin Roth f6ba75c736 util/lint/lint-stable-019-header-files: add test
Add a test to make sure that the linter fails correctly.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I971951d4248dd10abe4c622025fdaf86e014c6cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06 17:58:57 +00:00
Martin Roth cd9110b6d2 util/lint: Add rules.h & compiler.h to 019-header-files linter
The rules.h & compiler.h includes were removed in previous commits, so
add the checks to keep them out to the linter.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06 17:58:31 +00:00
Martin Roth 8a3f5a1d0b util/lint: ignore util/goswid, a new submodule
git submodules should be ignored when parsing the coreboot tree for
lint errors. Those should be handled in their own commit checks.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I62b58f0c536312fe4677855bca8f44bc7d3ebc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-05 19:38:12 +00:00
Karthikeyan Ramasubramanian 0dd3cf4534 util/amdfwtool/amdfwread: Fix incorrect option index
index I/O argument to getopt_long is not the index to argv. Instead it
is an index into the optlong array corresponding to the parsed option.
Also getopt() uses a global variable optind to track the index of the
next argument to be processed. Use the optindex variable as an index to
extract the filename from argv.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Change-Id: I33c74a0c8e12c5af76954524cf7294b7541d286b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66553
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04 17:06:21 +00:00
Caveh Jalali 7dd42da9a0 util/spd_tools: Rebuild utils when source changes
This adds source file dependencies to utilities so that they are rebuilt
when the source is changed. Previously, binaries were only built if they
did not already exist and never rebuilt to reflect source file changes.

BUG=none
TEST=verified binaries are rebuilt when source files are touched.

Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-04 16:57:33 +00:00
Martin Roth d12e4f5088 util/lint: Add lint tests to make sure they fail correctly
Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-04 16:43:50 +00:00
Martin Roth 8b45c1244e util/lint/lint: Reformat usage
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I684d374bd02a42e178383c26936e137e173f8f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-03 23:50:15 +00:00
Martin Roth 8ea8d856f3 util/lint/lint: Add command line parsing
The lint script just did very basic argument parsing and required the
sub-command and --junit argument to be in specific locations.  I'm
adding additional commands, so the first step is to add true command
line parsing.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7118c29e6c5d785b35a7ae12cf5984c43ebc3ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67191
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-03 23:49:53 +00:00
Julius Werner d96ca24652 cbfs/vboot: Adapt to new vb2_digest API
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new
hwcrypto_allowed argument, to potentially let them try to call the
vb2ex_hwcrypto API for hash calculation. This change will open hardware
crypto acceleration up to all hash calculations in coreboot (most
notably CBFS verification). As part of this change, the
vb2_digest_buffer() function has been removed, so replace existing
instances in coreboot with the newer vb2_hash_calculate() API.

Due to the circular dependency of these changes with vboot, this patch
also needs to update the vboot submodule:

Updating from commit id 18cb85b5:
    2load_kernel.c: Expose load kernel as vb2_api

to commit id b827ddb9:
    tests: Ensure auxfw sync runs after EC sync

This brings in 15 new commits.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02 23:51:29 +00:00
Felix Singer b45b48de73 util/docker/coreboot-jenkins-node: Install cmocka
flashrom uses cmocka for unit testing. Install it so that the CI can
use it.

Change-Id: I5c168e480d6f4cbfbbd175ecb035c88bfcbac00b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67272
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02 18:48:13 +00:00
EricKY Cheng 20f092d339 util/spd_tools: Add AMD Mendocino (MDN) platform
This patch adds support for MDN platform to the spd_tools.
This change replaces SBR with MDN.

BUG=b:243337816
TEST=Able to generate SPD for LP5 DRAM part.

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: If099af36de8a64e96fbfde32eaf15990f4b330c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-30 14:53:05 +00:00
Zheng Bao c88f2b5be7 amdfwtool: Fix indentation
Change-Id: I4c57c9bade318d54315f9692cd37edb694e33aa9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58320
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29 22:52:59 +00:00
Martin Roth 2dd74906e4 util/futility: Ignore deprecated declarations in OpenSSL 3.0
Building futility with OpenSSL 3.0 (default in latest Debian sid)
results in a number of warnings that various declarations have been
deprecated.  Since we (and futility) have warnings as errors enabled,
this causes the building of futility to fail, killing the entire
coreboot build.

To work around this until futility is updated, turn off the warnings
about deprecated declarations.

Bug 243994708 has been filed to get futility updated.  This workaround
can be removed when futility builds cleanly with the latest libsssl-dev.

BUG=b:243994708
TEST=Futility build doesn't fail with libssl-dev > 3.0

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I54e27e09b0d50530709864672afe35c59c76f06e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
2022-08-29 18:34:18 +00:00
Felix Singer feab41b030 util/docker/coreboot-sdk: Install GNAT 12
For some reason GNAT 11 is not able to build GNAT 12, since there are
some Ada errors during the compilation. However, it works with GNAT 12.
So use GNAT 12 for the host toolchain instead.

Change-Id: If00a05a0c8564e624809268a12fae28261e380a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-27 16:01:52 +00:00
Felix Singer acbdc4d72e util/docker/coreboot-sdk: Replace package qemu with qemu-system
The qemu package doesn't exist anymore or it was renamed. Instead of
installing QEMU for all available architectures, install only the
packages which ship architectures that are supported by coreboot.

  * qemu-system-arm
  * qemu-system-misc (for RISC-V)
  * qemu-system-ppc
  * qemu-system-x86

Change-Id: Ifc46a8c9fcb1ab3c38dc8cbbc906882e93a719d7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-27 16:01:12 +00:00
Tom Hiller a0eb855ef4 util/docker/coreboot-sdk: Remove doxygen
Doxygen was removed at the project level.  Remove the doxygen Debian
package and make target.

Change-Id: Ib82ba7890e7f53357eeca318b5f844164747aecd
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67039
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27 15:50:50 +00:00
Ritul Guru 9a321f31c8 util/amdfwtool: Add changes to reserve BIOS SIG
changes to reserve space for AMD_BIOS_SIG when
BIOS image is signed with RTMSignature.

Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-26 16:04:51 +00:00
Robert Zieba 65fe21f1c9 util/apcb/apcb_v3_edit: Add support for LP5X SDRAM
This commit adds support for LP5X SDRAM.

BUG=b:242765117
TEST=Ran with LP5X SPDs and manually patched APCB

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I2d3cb9c9a1523cb4c5149ede1c96a16c3991a5d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66840
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25 00:49:52 +00:00
Robert Zieba c4d77128c5 util/spd_tools: Add support for LP5X SPDs
This commit adds support for LP5X SPDs. The SPD format is identical to
LP5 except that the memory type is set to 0x15 instead of 0x13. Since
they are essentially the same, LP5/5X parts share the same parts JSON
file and SPD directory. LP5X parts are distinguished by the optional
`lp5x` attribute. This commit also updates two existing LP5X memory
parts with the correct attribute.

BUG=b:242765117
TEST=Generated SPDs, verified that SPDs generated from LP5X parts match
their LP5 counterparts except for memory type byte.

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-25 00:48:46 +00:00
Felix Singer bbe0a99d66 lint-000-license-headers: Add src/sbom/TAGS to exception list
Commit 6dac0c54cd makes the linter checking for license headers on all
files from the src directory. Since this TAGS file doesn't have one,
it's causing a linter error and it makes the QA system complain.
However, the TAGS file doesn't need a license header and thus add it to
the exception list.

Usually the build tests detect such issues, but commit 1d7a9debf2,
which introduced that file, was merged independently from the other
commit, which modifies the linter. Also, the patch that is introducing
this file was based on an older commit at which the patch modifying the
linter wasn't merged yet and so this issue was hidden.

Change-Id: I78da3fa70c39b709478a384da8769fc058ca18ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66938
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22 20:51:32 +00:00
Felix Singer 88ffed3df8 util/crossgcc: Remove binutils related MIPS patch
coreboot doesn't support the MIPS architecture anymore. So remove the
MIPS patch.

Change-Id: I62a2bca141b42ac33b628c48c84422570f4dda10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-22 16:18:35 +00:00
Maximilian Brune 1d7a9debf2 Add SBOM (Software Bill of Materials) Generation
Firmware is typically delivered as one large binary image that gets
flashed. Since this final image consists of binaries and data from
a vast number of different people and companies, it's hard to
determine what all the small parts included in it are. The goal of
the software bill of materials (SBOM) is to take a firmware image
and make it easy to find out what it consists of and where those
pieces came from. Basically, this answers the question, who supplied
the code that's running on my system right now? For example, buyers
of a system can use an SBOM to perform an automated vulnerability
check or license analysis, both of which can be used to evaluate
risk in a product. Furthermore, one can quickly check to see if the
firmware is subject to a new vulnerability included in one of the
software parts (with the specified version) of the firmware.
Further reference:
https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/

- Add Makefile.inc to generate and build coswid tags
- Add templates for most payloads, coreboot, intel-microcode,
  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
  intel ME and compiler (gcc,clang,other)
- Add Kconfig entries to optionally supply a path to CoSWID tags
  instead of using the default CoSWID tags
- Add CBFS entry called SBOM to each build via Makefile.inc
- Add goswid utility tool to generate SBOM data

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-22 14:48:46 +00:00
Felix Singer 61b90b173d util/nixshell/toolchain: Update GNAT to version 12
Change-Id: I308dc7640e16b7cfb7679d81099d8896f3f454fc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-18 17:03:10 +00:00
Martin Roth 957fde633b util/lint: Check files of all sizes for licenses
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib97d009c056b487136f20e5341b31183c65ef761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-17 19:44:08 +00:00