Commit Graph

49432 Commits

Author SHA1 Message Date
Felix Singer c28302fdda docs/releases/4.18: Rephrase deprecation note of Intel Ice Lake
The release of coreboot 4.18 is delayed and thus version 4.19 won't be
released in upcoming November. Instead, just mention the version to be
more flexible about the date.

Change-Id: I33213479b02c2159beca78432aca775a04409e4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68261
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12 00:28:10 +00:00
Felix Singer ad11533458 docs/releases/4.18: Deprecate Intel Quark and Intel Galileo
The SoC Intel Quark is unmaintained and various efforts to revive it
failed. Thus, deprecate the following components with the 4.18 release.

  * Intel Quark SoC
  * Intel Galileo mainboard

The support for these components will be dropped with the release 4.20.

Change-Id: I738ad74da043649107473dc0c2e6adf343e4cd35
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68260
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12 00:21:20 +00:00
Tim Crawford 8fdfa30255 mb/system76: Set gfx register
Fixes brightness controls on Windows 10.

Change-Id: I33ac1b5a17c95dbb1b166c38fcd639cdac439724
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-10-11 16:35:39 +00:00
Tim Crawford e086d149ce mb/system76: Set SMBIOS wakeup type to power switch
Windows hardware tests require this field not be "Reserved".

The System76 EC firmware does not report the wake type, so it is not
possible to know if the system was powered on from the power switch or
Wake-on-LAN. In the case WoL is used, this will report the wrong value.

Change-Id: I4653c6bce2a5f0a88281fc810df5646e44f90674
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-10-11 16:35:11 +00:00
Sean Rhodes 148f075264 mb/starlabs/starbook/kbl: Use chipset.cb aliases
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2da15db3d7fba4396c74800e531476c108cafe17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67421
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11 14:49:10 +00:00
Sean Rhodes 558eafd5b0 mb/starlabs/starbook/cml: Enable SRAM
Enable SRAM in devicetree so that resources are allocated properly
for it.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1d7ee4f950b31f2be6fb7bd107b5fe54785ed81a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67420
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11 14:47:49 +00:00
Sean Rhodes 60fb9350be mb/starlabs/starbook/cml: Enable P2SB
Enable the P2SB so that the SPI is discoverable by the OS.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ied7a6ea706e6da86182c109ab4813fa3fcebb1f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67419
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11 14:46:41 +00:00
Arthur Heymans ee0f5d794d util/amdfwread: Fix cookie error message
Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-11 14:45:09 +00:00
Arthur Heymans aafbe136a9 util/amdfwutil: Order enum and use hex consistently
This makes it easier to match the code to the datasheet (55758, NDA
only).

This also removes the duplicate lines:
"{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH |
PSP_LVL2_AB },
{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH |
PSP_LVL2_AB },"

TESTED: google/vilboz still boots.

Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-10-11 14:44:31 +00:00
Meera Ravindranath ac08e8fa8c mb/google/brya/nivviks: Enable ISH driver and firmware name
BRANCH=none
BUG=b:234776154
TEST=build and boot Nirwen UFS, copy ISH firmware to host
file system /lib/firmware/intel/adln_ish.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-11 14:44:06 +00:00
Angel Pons 160e5a963d mb/prodrive/hermes: Make board settings less error-prone
First of all, make sure that `get_board_settings()` never returns NULL.
If there's a problem, return predefined values for board settings.

If the board settings definition differs between coreboot and the BMC,
the CRC will not match. Allow coreboot to use the BMC settings provided
by older BMC firmware revisions which have less settings, if the CRC of
the first N bytes matches the expected CRC.

TEST=Boot coreboot master with BMC FW R04.05, observe board settings
being honored even though coreboot's definition has an extra option.

Change-Id: I0f009b21ef0850a2af6edef1818c770171358314
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67381
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11 14:43:45 +00:00
Sean Rhodes 716bd48a53 payloads/edk2: Add a recipe to build UniversalPayload.elf
Add a recipe to build UniversalPayload.elf, which uses a wrapper for the
UniversalPayloadBuild.py that is hosted in the edk2 repository.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2aa318513244f576e07e72713fad3b4f7bd7c22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-11 14:42:39 +00:00
Martin Roth 461c33b226 coreboot: Add support for include-what-you-use
The tool "include-what-you-use" analyzes each file's headers and makes
recommendations for header files to add and remove.  There are
additional scripts as part of the package that will make these changes
directly based on the recommendations, but due to the way coreboot
compiles code in/out base on Kconfig options, this isn't really safe for
the project to use.

It is a good starting point though.

To use, set the IWYU kconfig option, then build with the command:

make -k

Because this doesn't actually build any files, the -k option is needed
or make will stop after looking at the first file.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I084813f21a3c26cac1e4e134bf8a83eb8637ff63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-11 14:33:28 +00:00
Michał Żygowski 21dc639f99 configs/config.msi_ms7d25: Enable CBFS serial and UUID as default
There is no option to calculate or generate the serial number and UUID
on this platform. Enable CBFS UUID and serial by default so anybody
can easily populate the missing fields.

TEST=Add UUID and serial CBFS files, boot the platform and see both
UUID and serial number are populated correctly.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic8af889f12617d4ab6a27c6f336276c04f26244c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64640
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11 08:36:33 +00:00
Michał Żygowski a3bd8e9618 drivers/generic/cbfs-uuid: Add driver to include UUID from CBFS
When system_uuid CBFS file is present and contains the UUID
in a string format, the driver will parse it and convert to binary
format to populate the SMBIOS type 1 UUID field.

TEST=Add UUID file and boot MSI PRO Z690-A DDR4 WIFI and check with
dmidecode if the UUID is populated correctly.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I22f22f4e8742716283d2fcaba4894c06cef3a4bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64639
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11 08:36:06 +00:00
Subrata Banik 0c14c0c585 mb/google/rex: Enable PD Sync
This patch enables PD Sync for Rex.

BUG=b:248775521
TEST=Able to boot Google/Rex with PD sync enabled.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I749b5dea481c7546579e97f923f143dd17f831d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67819
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-10-11 03:24:01 +00:00
David Wu 91fb8ca7e7 brya: add new zydron variant
Add a new zydron variant, which is a variant of brya's skolas
baseboard. currently copy the variant file from kano.

BUG=b:250787251
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I49a41678568daef80b7cd1e3ed60ce4763034f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68130
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 22:46:00 +00:00
Elyes Haouas e8bb6d2b16 nb/intel/i945/raminit.c: Fix formatted print
Change-Id: I7122988a1c88175a2e72c11bb95bfa434ce48ff2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:52:16 +00:00
Nicholas Chin 89d6d2b82c Documentation/flashing_firmware: Add info about SPI flash header
Some mainboards have a header connected to the SPI bus, which can be
used to connect a second flash chip and override the onboard flash. This
allows one to boot coreboot on the system without ever having to flash
the onboard flash. HP boards with this header all seem to use the same
2x8 or 2x10 header layout, so document the pinout.

Change-Id: Ic2bf1244adfb78872340f212519c6ab33e26646a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67818
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:51:43 +00:00
Fred Reitberger 7e9801171e util/amdfwtool: Add Mendocino to usage
Add missing Mendocino soc to usage print.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:50:44 +00:00
Martin Roth 3c963d9e88 mb/amd/birman: Add framework for morgana crb birman
birman is the reference board for the morgana SoC.  It needs to be
updated to match the actual board design as well.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I4b16854c954949217a76c3d4f04ddc4001f64337
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68196
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:50:34 +00:00
Martin Roth f225d761ba soc/amd/common: Remove buildtime error for unknown cpu
This is not critical functionality and doesn't need a build-time error.
Having it as a build time error causes a chicken & egg issue where
the chipset needs to be added before it can be added to this file, but
the header file fails the build because the chipset is unknown.

It's not practical to exclude these files from the new platform builds
because the PSP functionality is thoroughly embedded into the coreboot
structure.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib02bbe1f9ffb343e1ff7c2bfdc45e7edffe7aaed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-10 21:50:20 +00:00
Martin Roth 1a3de8e5bc soc/amd/morgana: Add initial commit for new SoC
This is an initial framework for the Morgana SoC.

TODOs have been added to the files for both customization and
commonization.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: If92e129db10d41595e1dc18a7c1dfe99d57790cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68195
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:48:30 +00:00
Martin Roth 134908381f util/amdfwtool: Add preliminary code for morgana & glinda SOCs
This allows amdfwtool to recognize the names for the upcoming morgana
and glinda SoCs.  It does not yet do anything for those SoCs, but this
allows the morgana SoC to build.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:45:07 +00:00
Sean Rhodes a46fd86910 payloads/edk2: Guard the build target
Specifying a build target only applies to UefiPayloadPkg, so guard it
against the relevant Kconfig option.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia4597b5ed76616e39cec45f8a69be9f1ccd72d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-10 21:44:36 +00:00
Sean Rhodes 3c16616725 payloads/edk2: Guard the silent switch
The silent switch, `-s`, only works for building UefiPayloadPkg. Guard
it against the relevant Kconfig option so that it doesn't cause
problems with other targets.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5a5df636e6484a435c849c6d19c7cb61e8e62ee6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68181
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:44:26 +00:00
Fred Reitberger 743c1c0894 util/lint/lint-stable-003-whitespace: Fix shell variable name
Fix shell variable "LINTDIR" so that helper_functions.sh can be found.

TEST=`./util/lint/lint lint-stable --junit` no longer prints "cannot
open /helper_functions.sh: No such file"

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I68f2e65fa1c9297ad6b58b77576deaeef8bd76e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-10 21:43:47 +00:00
Nicholas Chin c468641917 Docs/architecture: Fix filename for coreboot architecture diagram
A spelling mistake in the markdown reference to the coreboot vs EDK II
bootflow diagram was previously fixed, but the actual filename was not
changed resulting in a broken reference.

Change-Id: I512646e9af312ba2e1db8f597f6fffa8d54a3515
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67782
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-10 07:25:19 +00:00
Karthikeyan Ramasubramanian 79e8cd9809 soc/amd/mendocino/psp_verstage: Remove TODO comment
PSP verstage has been successfully enabled and this makefile looks good.
Hence removing a TODO comment.

BUG=b:239090306
TEST=Build Skyrim BIOS image.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic3cd55171fd1e4d74fac72f0b0b92dc80e533b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-08 21:09:08 +00:00
Chao Gui d171e7f12b mb/google/skyrim: Create frostflow variant
Create the frostflow variant of the skyrim reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_FROSTFLOW

Signed-off-by: Chao Gui <chaogui@google.com>
Change-Id: I937e6562094968824e73bfa20390b3ec8b24dfa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-08 21:08:32 +00:00
Angel Pons 373517cdeb mb/prodrive/hermes: Write reset cause regs to EEPROM
Write the value for reset cause registers to the EEPROM for debugging.

Change-Id: I827f38731fd868aac72103957e01aac8263f1cd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67483
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-08 21:07:46 +00:00
Angel Pons c960564811 mb/prodrive/hermes: Add part numbers to SMBIOS
Adjust the EEPROM layout to account for two new fields: board part
number and product part number. In addition, put them in a Type 11
SMBIOS table (OEM Strings). Also, rename a macro to better reflect
its purpose.

Change-Id: I26c17ab37859c3306fe72c3f0cdc1d3787b48157
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67759
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-08 21:06:08 +00:00
Angel Pons f007ab7b43 util/inteltool: Add support for (non-ULT) Broadwell
Add support for traditional (non-ULT) Broadwell.

Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08 21:04:43 +00:00
Angel Pons aa4cd73409 util/inteltool: Add 9 series PCH support
Add the PCI device IDs for 9 series PCHs.

Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08 21:03:58 +00:00
Sean Rhodes d750875cde payloads/edk2: Add note that upstream edk2 does not work
Upstream edk2 doesn't work, but we still have the option for it
for testing.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6ec9f4746640baa030762650ab7b83d85ab8c1e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-08 21:01:22 +00:00
Sean Rhodes 0d6dc48f01 payloads/edk2: Add an option for verbose builds
Add EDK2_VERBOSE_BUILD which removes the `-q` and `-s` switches
so the build log becomes verbose.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iaf1e96657f43edddfa4de0d3e00f3b24e7eb855b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67677
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-08 21:00:55 +00:00
Martin Roth 87bbeac2eb vc/amd/fsp: Add Morgana FSP vendorcode
Initial commit of the FSP-specific code for the Morgana SoC.

This is just an initial framework and still needs to be updated
to match the Morgana FSP.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ic53c59404f96c73c55eb2648113c5ced26d6e20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08 20:58:58 +00:00
Martin Roth 8834040069 vc/amd/fsp: Make common directory
The common directory is for files that shouldn't change, or shouldn't
change much between platforms.

These will be removed from other directories and used in upcoming
commits.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08 20:58:33 +00:00
Martin Roth c9205c57ea Update amd_blobs submodule to upstream master
Updating from commit id 43136aa:
2022-09-30 11:01:39 -0700 - (mendocino: Add stripped microcode patch)

to commit id 234dc70:
2022-10-06 16:05:45 -0700 - (morgana: add placeholder blobs)

This brings in 3 new commits:
234dc70 morgana: add placeholder blobs
84928ce mendocino: Upgrade SMU to 90.35.0
12ca1df mendocino: Add all blobs from PI 1.0.0.2

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Id55c468721ac42ecd71e8e3d1fa1cb4887a98c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08 20:58:14 +00:00
Sean Rhodes 7202365160 Documentation/releases: Add details about edk2 updates
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I592f0ee971737ef271d1df9142551eb24b775a06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-08 20:57:53 +00:00
Sean Rhodes 91564fc370 payloads/edk2: Separate the build target and repository
Until recently, there were two options to build edk2, UefiPayloadPkg and
CorebootPayloadPkg. Now, there is only one, UefiPayloadPkg but soon,
there will be Universal Payload.

It makes more sense, as the official edk2 repository doesn't work with
coreboot, to have the build target and repository separate. That will
allow for building either UefiPayloadPkg or Universal Payload from the
official repository, MrChromebox' fork or a custom repository.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If7f12423058ef69838741f384495ca766ccea083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-08 20:57:20 +00:00
Kevin Chiu 325afdaf9f mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbon
Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbon

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I74cd634700b2de16ae471e0a738b67a14fd82a50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68168
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-08 20:55:12 +00:00
Sean Rhodes 8956b1af59 ec/starlabs/merlin: Add EC related files for Alder Lake boards
Add EC memory layout and Q events for Intel Alder Lake based boards,
the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE
5570E.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8cea386ba91d076084002738fe7041834deea311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-07 22:09:59 +00:00
Angel Pons b9af5133dd mb/prodrive/hermes: Factor out serial reading logic
Add the `eeprom_read_serial()` function to read serials from the EEPROM.
Note that there's only one buffer now: this means only one serial can be
accessed at the same time, and the buffer needs to be cleared so that it
does not contain old data from other serials. Given that the serials are
copied one at a time into SMBIOS tables, having one shared buffer is not
a problem.

Change-Id: I5c9781e4e599043be756514cfd6dd86dedcf580c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67275
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 22:08:11 +00:00
Angel Pons a39a812e40 mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail
The PCH's SGPIO pads are connected to a buffer chip that is powered from
the always-on +3V3_AUX rail. For some cursed reason, when the SGPIO pads
stay configured as SGPIO when a Poseidon system shuts down, voltage from
the +3V3_AUX-powered buffer chip will leak into the +5V rail through the
SATA backplane. Just pulling the SGPIO pads low before the system powers
off stops the +5V rail from being cross-powered.

This issue has only been observed in S5, but it's very likely other
sleep states are affected as well. Thus, always pull the SGPIO pins
low before entering ACPI S3 or deeper because the power supply will
turn off in these states as well.

TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered
     after going to S5. We measured 0.17V on our system, but voltages as
     high as 0.6V were measured on other systems. Verify that unplugging
     the SGPIO cable going to the SATA backplane results in the +5V rail
     voltage dropping to 0V, which indicates that the voltage leakage is
     exclusively coming from the SGPIO and SATA backplane. Finally, make
     sure that the +5V rail voltage drops to 0V after going into ACPI S5
     with this patch applied and the SGPIO cable connected.

Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07 22:07:08 +00:00
Sean Rhodes 3c3516b874 util/coreboot-configurator: Update the README
Update the README with new instructions for Debian 11 and MX Linux.

Also add the build dependencies.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-07 22:06:06 +00:00
Sean Rhodes c436541c3d soc/intel/apollolake: Add UFS Interrupt
According to Intel document number 336561, GLK has UFS (0x1d),
so add the PCI interrupt.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 22:05:11 +00:00
Sean Rhodes 0eb165adf7 soc/intel/apollolake: Remove SD Card interrupt for GLK
According to Intel document number 336561, G, SD Card (0x1b)
does not exist on GLK, so remove it.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 22:04:46 +00:00
Mario Scheithauer d78722f2f8 mb/siemens/mc_ehl2: Use preset driver strength for SD-Card
The intention of predefining driver strength is to avoid that the OS
SD-Card driver changes this setting.

Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-07 22:03:54 +00:00
Mario Scheithauer c8c64c12a5 soc/intel/ehl: Set Ethernet controller to D0 power state
To be able to change the MAC addresses, it is necessary that the
controllers are in D0 power state. As of FSP MR3, Intel has set the
controllers to D3 power state at the end of FSP-S TSN GbE
initialization. This patch sets the state back to D0 before the
programming of the MAC addresses.

Test:
- Build coreboot with FSP MR4 for mc_ehl2 mainboard
- Boot into Linux and check MAC addr via 'ip a'

Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07 22:03:45 +00:00