Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to
libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the
__weak function.
ARM platform usually does not have common address for PCIe to access the
configuration space of devices. Therefore, new API is added to pass the
base address of PCIe controller for payloads to access PCIe devices.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
We wrote to the wrong register. The EN bit is in the CC (Controller
Configuration) register at 0x14.
Fixes re-initialization in QEMU and on siemens/chili during a second
FILO run.
Change-Id: I125de55d7f1a7c9f070437190c5a08a288b274f8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We only need to know if the NVMe command set is supported. Other
command-set bits can be set too, but we don't have to care.
Fixes init in QEMU which has more command-set bits set by now.
Change-Id: I29a693cf8cc13775e94dc671e8d0412ad86fef9c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We mustn't try to release resources that we haven't acquired yet. Also,
sending commands to the NVMe device is futile if we already timed out.
Fixes hangs after a failed init noticed in QEMU and on siemens/chili.
Change-Id: Ib83c7785d6e0dc3c44fbd50a30694c74932750d6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t
lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no
longer needed.
Also replace 'struct cbuint64' with 'cb_uint64_t' and remove
'cb_unpack64' in libpayload for compatible with lb_uint64_t.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h
Remove redundant defines from libpayload.h and libpayloads' standard
headers.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Include paths fixup macro for vboot was broken and was adding
unnecessary prefix to paths from $(coreboottop). This patch adds correct
filters to fix this behavior.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
coreboot recently introduced non-printable loglevel markers in the CBMEM
console. Payloads were generally unaffected since they don't use log
levels and it is still legal to append lines without a marker to the
log. However, payloads using cbmem_console_snapshot() to display
existing logs from coreboot have started seeing '?' characters in place
of the markers. This patch fixes the issue by filtering out marker
characters.
BUG=b:221909874
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4a9e5d464508320cf43ea572d62896d38c2a128d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
TPM1_MODE and TPM2_MODE defines have to be added to vboot and payload
cflags to make them build correctly without requiring payloads to provide
defines.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I567a9f04d7089699840dc7e0a063cf3030fb934b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
To be able to link libcbfs without vboot, we need garbage
collection now.
Change-Id: Id9a9fe7efb9fb4409a43ae8357f4f683618805d2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Casts from integer to pointer are usually a case for phys_to_virt().
Change-Id: I861d435ff2361cdc26a2abd46d43b9346fa67ccc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Lack of strip made it required to pass arguments to the
kconfig-to-binary macro without spaces. Strip fixed invalid behavior of
this macro.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I9889b45f773b9675fae287086d324c180c505a4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
CBFS MCache size was assigned a value of the coreboot tables entry size
instead of the MCache size.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I8a8c3a10c6032121b4c5246d53d2643742968c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Don't assume that libpayload is built from a fully checked
out coreboot tree.
There's already an override when building vboot, so reuse
that override when referring to its header files.
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I503c69a593dd68b3a974fbdbb64d7bb25d6c7f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Rob Barnes <robbarnes@google.com>
llvm-ar does not support "open" script command, and fails with an error.
This patch fixes it by removing lines `$(AR) rc <object-files>` and
it puts them as "addmod" commands. This way all object files and
archives can be packed into one archive.
Change-Id: I0c53d1d613b5edc321e268d1d996fac3146680f8
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
New CBFS API uses commonlib/bsd/cbfs_serialized.h, which includes
vboot's vb2_sha.h. And, because vboot's includes are not available
in libpayload's installation directory nor in lpgcc paths, it was
causing compilation errors. This patch fixes this issue.
lpgcc will look for `vboot` directory like it is doing for `include`
directory to create correct paths. However, if payload will be built
using libpayload's build dir as a base, then vboot headers from
3rdparty/vboot will be used, as there is no way to pass VBOOT_SOURCE
from makefile to lpgcc.
Moreover, this patch moves VBOOT_SOURCE to the main Makefile to
make it available for installation target, to install headers from
vboot directory provided by caller.
Change-Id: I68dd7e1545cfcaf24547d8a9fe289447c79da222
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reported-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The goal when adding the new CBFS API in CB:59497 was that the old CBFS
code would be left completely untouched and just moved to the side a
bit, so that it could continue to work for the payloads that use it
until they all have time to transition to the new CBFS API.
Unfortunately, between the different iterations of the patch something
went wrong with that and the final committed version of cbfs_legacy.c
does differ in some parts from the original code, including a changed
macro definition that breaks decompression support. This patch restores
all the legacy CBFS files to exactly what they used to be (other than
the necessary changes in cbfs_core.h to avoid double definition
clashes).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic7fd428acb03d3830f66f807cd1d7cdbd652f409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
CBFS_VERIFICATION was depending on the VBOOT instead of on VBOOT_LIB,
which made enabling CBFS_VERIFICATION impossible. VBOOT is not
available, like in the main coreboot, but is was changed to VBOOT_LIB,
and was not correctly adjusted in patch instroducing CBFS_VERIFICAITON
option.
Change-Id: Ie23bad5f0ed3faf17a2ed7a3ad99310ee803edd2
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch introduces equivalents of unverified_area CBFS access
functions added to the main coreboot tree in CB:59678
Change-Id: Ibadfd2a5cb6ad037ef1222b0a4301f90a79a127b
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit adds new CBFS API, which is based on the one available in
the main coreboot source tree. Libpayload implementation supports RO/RW
file lookups and file contents verification.
Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch introduces building and linking of 3rdparty/vboot with
libpayload. VBoot can be enabled by setting CONFIG_LP_VBOOT_LIB.
Moreover it can be configured to use either TPM or TPM 2.0 mode,
and whether to use SHA256 processor extension instructions on x86.
Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch introduces new FlashMap API, the fmap_locate_area().
It works on cached FlashMap provided in lib_sysinfo.fmap_cache.
Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
coreinfo and nvramcui are using libpayload/bin/lpgcc and libpayload
build directory as a base, instead of installing it first. This caused
include errors, because commonlib/bsd is not present there. This patch
introduces comonlib/bsd include path to lpgcc CFLAGS if it is being
built using libpayload build directory as a base.
Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When compiling libpayload using x86_64 toolchain for ARCH_MOCK compiler
reports an error about gerring address of packed member. Until now it
had to be disabled by passing -Wno-address-of-packed-member to
EXTRA_CFLAGS. This patch disables this warning.
Change-Id: I9a948fabe66f7297632ecaca8ec1bfa5c842b750
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Implement __fls() as an alias for log2(), and remove the duplicate
definitions in commonlib/storage/sdhci.c.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch adds a new way of implementing flash access for libpayload.
Until now all reads had to be performed using cbfs_media, which is
obsolete. From now on all reads should be performed using
boot_device_read().
This patch also provides a default implementation of boot_device_read()
for x86 architecture.
Change-Id: I1babd2a8414ed9de3ca49903fcb4f036997b5ff3
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch ports some parts of main coreboot Makefile to the libpayload
Makefile in order to improve object files creation.
Moreover, the coreboot source files are now accessible an will be
correctly compiled under libpayload build directory.
Change-Id: If1280c0a3f7e99aad2ecf8a0379a98af31ccefc3
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Copy header files from the main commonlib/bsd to libpayload output
installation directory.
Change-Id: Idc7175240f3077ec98280331f9a952310aae4341
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Unit tests fail on clang 13.0 because Cmocka's main() function is
declared with return type int, but through some of our chain-include
games it sometimes gets coreboot's main_decl.h which declares the
function as void. Compilers have traditionally always been very
laissez-faire about the signature of the main function, but it seems
that clang has been getting more strict by default recently. Explicitly
disable the related warning to shut it up.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I867c9dac659be86e7b7cf4cc41d6fa105aa9ac41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Unit tests fail on clang 13.0 with a cryptic
error: _timestamp_size changed binding to STB_WEAK [-Werror,-Wsource-mgr]
Probably something related to the weird things we do to mock memlayout
areas. Too lazy to track it down. Let's just disable this
(clang-specific, not properly documented) warning flag.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie49c9eef3c74592c068c899c6717621dbcb9f609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Remove unnecessary escape bachslashes from:
addr="$(echo \"$$$$sym_line\" ...
The 'echo' will print output line with double quote characters, which
then will be included in the values passed to --add-symbol. This can
cause errors.
Change-Id: I6023515191d6c236bf57870159a35d518f25e9d8
Reported-by: Yu-Ping Wu <yupingso@chromium.org>
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
coreboot stores much information in the CBMEM IMD. Until now it was
ignored. This patch makes use of these coreboot tables entries.
It also removes get_cbmem_addr() function as it is no longer needed.
Moreover, the coreboot tables entry CB_TAG_MRC_CACHE does not exist
anymore, as it is not created by the code. It was replaced by
CBMEM_ID_MRCDATA entry, so MRCDATA should now be accessible through
sysinfo structure field.
Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Make BSD part of the coreboot commonlib accessible to libpayload.
Change-Id: I09f475d399ab785f3d3ffdb4b42950d2b397845e
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
There were escape backslashes around regular expression passed to grep.
Because of that, grep was returning empty results as a consequence of
pattern mismatch, and thus symbols pointing to original functions were
not created correctly.
Change-Id: I751109735b6c56824df9a560ae989bf062a0e9a6
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some unit tests might require catching assert failures. This patch adds
an assert() variant depending on __TEST__ define passed to unit tests.
Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some files in tests/include/mocks might have the same name as main
libpayload include files. Remove this path from default includes to
force addition of mocks/ prefix in include paths. This will help
avoiding name clashes and will also make mock headers visible.
Change-Id: I4baa07472f0379d56423cf7152b1ecc9a4824539
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Move th x86 I/O functions declarations from tests mocks to the mock
architecture io.h. This will make x86 I/O-dependent tests simpler,
because the x86_io.h from mocks will not have to be included manually.
Change-Id: Ie7f06c992be306d2523f2079bc90adf114b93946
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit adds a unit-tests framework ported from coreboot, and test
for drivers/speaker. Usage of the unit-tests framework is same as for
the coreboot one.
Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Mock architecture can be used to build libpayload using host compiler.
It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets
LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs.
Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools
provided by xcompile.
Mock architecture configuration can be used by payloads for testing
purposes. Thanks to it, tests can be architecture-independent,
and can be executed without requiring compatible Kconfig options,
e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide
implementation for most architecture-specific functions present
in arch/* directories.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Instead of setting each pixel in the framebuffer, use memcpy() to clear
screen faster. As this method should be fast enough, remove the fast
path using memset().
The speed of clear_screen() on brya (x_resolution = 1920,
bytes_per_line = 7680):
- Using memset(): 15ms
- Setting each pixel: 25ms
- Using memcpy(): 14ms
Also remove set_pixel_raw() since it's now used in only one place.
BUG=none
TEST=emerge-brya libpayload
TEST=Saw developer screen on brya
BRANCH=none
Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Move the locally declared typec_orientation enum from chip.h to
coreboot_tables.h.
Change enum typec_orientation name to type_c_orientation for consistency
with contents of coreboot_tables.h.
Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE.
BUG=b:149830546
TEST="emerge-volteer coreboot" and make sure it compiles successfully.
Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds type-c port information for USB Type-C ports to the
coreboot table. This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully. Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
localhost ~ # cbmem -c | grep type-c
added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The input buffer to the buffer_to_fifo family of functions is only read,
so it can be a const pointer. (Also, remove the MIPS check in libpayload
for these functions... the MIPS architecture has been removed a while
ago.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Before this patch EXTRA_CFLAGS were placed before many other options.
This made overriding impossible even, when necessary. This patch moves
EXTRA_CFLAGS to be placed after original CFLAGS, thus making option
overriding possible.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently clear_screen() calls set_pixel() to set all pixels. However,
the actual order of pixels being set depends on the framebuffer
orientation. With NORMAL orientation, the framebuffer is accessed
sequentially; with LEFT_UP/RIGHT_UP orientation, it is accessed back and
forth, leading to performance drop (>1 second on bugzzy).
Therefore, ensure sequential access to the framebuffer, regardless of
the orientation.
BUG=b:194967458
TEST=emerge-cherry libpayload
BRANCH=dedede
Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57104
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The timer structure (in particular, the offset to memory addresses)
on recent MTK SoCs for example MT8195 has been changed.
BUG=b:195274787
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifd6ff65a825c4309c47f3b115b80a8ecd42fedac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56845
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Building nvramcui with i386-elf-gcc (coreboot toolchain
v2021-04-06_7014f8258e) 8.3.0 and Link Time Optimization (LTO) enabled
in libpayload (`CONFIG_LP_LTO=y`) fails with the error below.
LPGCC nvramcui.bin
curses/PDCurses/pdcurses/refresh.c: In function 'wrefresh':
curses/pdcurses-backend/pdcdisp.c:217:4: error: 'bg' may be used uninitialized in this function [-Werror=maybe-uninitialized]
curses/pdcurses-backend/pdcdisp.c:214:18: note: 'bg' was declared here
curses/pdcurses-backend/pdcdisp.c:217:4: error: 'fg' may be used uninitialized in this function [-Werror=maybe-uninitialized]
curses/pdcurses-backend/pdcdisp.c:214:14: note: 'fg' was declared here
lto1: all warnings being treated as errors
lto-wrapper: fatal error: i386-elf-gcc returned 1 exit status
compilation terminated.
/opt/xgcc/lib/gcc/i386-elf/8.3.0/../../../../i386-elf/bin/ld.bfd: error: lto-wrapper failed
collect2: error: ld returned 1 exit status
`pair_content()` returns in case `PAIR_NUMBER(attr)` is invalid, so
guard the usage of `serial_set_color()`.
if (pair < 0 || pair >= COLOR_PAIRS || !fg || !bg)
return ERR;
Note, building with x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1
20210110 does *not* fail.
Change-Id: Ic63e34f2b5bc9f826db37597bebc6b20542481d7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This was originally several commits that had to be squashed into one
because the intermediate states weren't able to build coreboot:
- one to remove everything that wasn't our own code, leaving only
regex.[ch], toada.c, description.md and Makefile.inc.
- one to copy in Linux 5.13's scripts/kconfig and adapt Makefile.inc
to make the original Makefile work again.
- adapt abuild to use olddefconfig, simplifying matters.
- apply patches in util/kconfig/patches.
- Some more adaptations to the libpayload build system.
The patches are now in util/kconfig/patches/, reverse applying them
should lead to a util/kconfig/ tree that contains exactly the Linux
version + our own 5 files.
Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
CB:51638 separated Chrome OS NVS from global NVS by allocating it
separately in CBMEM. CNVS is used in depthcharge to fill firmware
information at boot time. Thus, location of CNVS needs to be shared in
coreboot tables for depthcharge to use.
This change adds a new coreboot table tag
`CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the
location of CNVS in CBMEM to payload (depthcharge).
Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the
end of GNVS instead of the fixed offset 0x1000. DNVS is used on older
Intel platforms like baytrail, braswell and broadwell and depthcharge
fills this at boot time as well. Since DNVS is no longer used on any
new platforms, this information is not passed in coreboot
tables. Instead depthcharge is being updated to use statically defined
offsets for DNVS.
BUG=b:191324611, b:191324611
TEST=Verified that `crossystem fwid` which reads fwid information from
CNVS is reported correctly on brya.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Kconfig option to set the keyboard translation state on exit and
set the default to true. This restores the keyboard to the power-up
defaults for firmware that does not always run libpayload keyboard init
to have consistent state, and provides an option to disable translation
for keyboards that might need it.
Change-Id: I25dfe3f425a5bb57e97476564886672b707aa3bd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If we select scancode set #1 and keep that, it can confuse Linux
with keyboards that don't return to set #2 when asked to load the
defaults. This happens for instance with various integrated Think-
Pad keyboards but was also seen with an external PS/2 one.
The chosen configuration, scancode set #2 without translation, seems
to be the default for many systems. So we can expect other payloads
and kernels to work with it.
Change-Id: I28d74590e9f04d32bb2bbd461b67f15014f927ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of ignoring keyboards indefinitely when they failed to
initialize, we wait 5s and then start over with the hotplug
detection. As we always assume a present keyboard at first,
we'd otherwise never have a chance to hot plug a device after
the initial 30s timer ran out.
Change-Id: I8dec4921b2e932442d52b5118cdcf27090633498
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
While we assume a keyboard is attached, we send an echo command every
500ms. If there is no data coming from the keyboard within 200ms, we
assume it was detached.
Correspondingly, if we assume no keyboard is attached, we run an echo
command once per second.
Change-Id: I2c75182761729bf30711305f3d8b9d43eafad675
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is already the case on x86 but not on the ARM platforms, and
{read,write}[bwl] are using volatile pointers, too, so follow suit.
Change-Id: I6819df62016990e12410eaa9c3c97b8b90944b51
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The new `Makefile.payload` can be included by the Makefiles of pay-
loads for in-tree builds. The basic idea is to use libpayload's
build results without the `make install` step, and to ensure that
incremental builds work. For instance, if libpayload's code changes,
a `make` for the payload would automatically update the libpayload
build and rebuild the payload. But if there are no code changes in
libpayload, only updated files of the payload will be re-built.
The configuration of libpayload is supposed to be automatically
generated from a `defconfig` file. If this `defconfig` changes,
libpayload and the payload will be re-built.
Change-Id: If5319f1bf0bcd09964416237c5cf7f8e59f487a2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47633
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add read64 and write64 for consistency with x86.
BUG=b:178785769
Change-Id: I342e3a23201d0b804ea5ecfe47ee3e4bb516de4c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It either doesn't exist (in-tree builds) or is the same as $_LIBDIR.
Change-Id: I9551cbfc3295d86c22a3785be7cdc0f65eeb08c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47632
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We only need `$_OBJ` in the include path for in-tree builds. Also,
curses only need special handling for those and PDCurses turned out
to need many more include paths.
Change-Id: Idd29ef33065033e26ba61b09d412d8ca3566d643
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of checking for an already fully build `libpayload.a`, we check
for the `libpayload.config` which is the actual prerequisite to start
using `lpgcc`. This will allow compilation of payload sources before or
in parallel with the build of `libpayload.a`.
Change-Id: Ic0143fefe33560af8b013ae48bbbe231b3ad46f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Introduce a `$_OBJ` variable, that points to the build directory for
in-tree usage of `lpgcc`. If unset, the default `../build` relative
to the location of `lpgcc` is used.
Change-Id: I35112d7533d69aa51252dd2bceec010a62522403
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47629
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This should make it easier to find the correct config for in-tree
builds.
Change-Id: I08d396ae3cedc65f63c4b8865701ea123c7d56cb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47628
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Keep libpayload's xcompile in its build dir. While we are at it,
align things with the top-level version.
Having `.xcompile` in a central place led to race conditions when
multiple payloads try to build their own libpayloads in parallel.
Change-Id: I504e1862db79b368289867f7568c9169f27a1549
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The keyboard self-test is required for some devices. At least one
device (integrated keyboard in a ThinkPad X201) actually starts the
test automatically leading to spurious output and no response for
the first seconds.
We wait up to 5s for the self-test result. On failure or timeout,
the command will be repeated until the 30s init timer runs out. This
happens all in the background of the UI polling loop.
To not unnecessarily delay the boot process, we first try an oppor-
tunistic initialization which skips the self-test.
Change-Id: Ie07b31e74d06e116ac81e76309621eed39a19b49
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Will be used to time out in states that don't always advance.
Change-Id: I28235e7638d8157cedf81fd915a41d28a1fc070b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We'll process the init sequence as part of the polling loop. This
should have several advantages:
* It eases error handling, i.e. we can return to an earlier state.
* We don't have to stall initialization when a keyboard takes a
little longer.
* Generally, these keyboards can be hot-plugged (albeit not by
design).
Change-Id: I9cf5cf31eb420b3994bec20e56a72d37f3d2996e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Draining the keyboard's buffer is only possible when the keyboard
port is enabled. We should also disable input scanning before, as
the buffer could be filled again with new keystrokes otherwise.
Change-Id: Ibac9c0d04880ff4a3efda5ac53da2f9731f6602c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move the input-buffer draining into a function. It uses the low-level
i8042 API directly to avoid conflicts with changes in the high-level
keyboard API.
Change-Id: I9427c5b8be4d59c2ee3da12d6168d34590043682
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even if we are careful, it's still possible that we read spurious
data from the keyboard, e.g. keystrokes. Namely, when we send the
reset/disable command, there is a race before the command is pro-
cessed.
So we should always process data from the keyboard in a loop. We
break it, when an ACK (0xfa) or a NAK (0xfe) is received, and warn
on unexpected data unless it might be due to the mentioned race.
This also gives us the opportunity to use command-specific timeouts
which we take from Linux: 1s for the keyboard self-test (as there
are keyboards that perform the test before acking the command) and
200ms for all other commands.
Change-Id: I60a2643a8ff4b9231c63bf970c8749c97c7d8926
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some background first: The original XT keyboards used what we call
scancode set #1 today. The PC/AT keyboards introduced scancode set #2,
but for compatibility, its controller translated scancodes back to
set #1 by default. Newer keyboards (maybe all we have to deal with)
also support switching the scancode set.
This means the translation option in the controller and the scancode
set selection in the keyboard have to match. In libpayload, we only
support set #1 scancodes. So we either need the controller's trans-
lation on and set #2 selected in the keyboard, or the controller's
translation off and set #1 selected in the keyboard.
Valid configurations:
* SET #1 + XLATE off
* SET #2 + XLATE on
Both with and without the PC_KEYBOARD_AT_TRANSLATED option, we were
only configuring one of the two settings, leaving room for invalid
configurations. With this change, we try to select scancode set #2
first, which seems to be the most supported one, and configure the
controller's translation accordingly. We try to fall back to set #1
on failure.
We also keep translation disabled during configuration steps to
ensure that the controller doesn't accidentally translate confi-
guration data.
On the coreboot side, we leave the controller's translation at its
default setting, unless DRIVERS_PS2_KEYBOARD is enabled. The latter
enables the translation unconditionally. For QEMU this means that
the option effectively toggles the translation, as QEMU's controller
has it disabled by default. This probably made a lot of earlier
testing inconsistent.
Fixes: commit a95a6bf646 (libpayload/drivers/i8402/kbd: Fix qemu)
The reset introduced there effectively reverted the scancode
selection made before (because 2 is the default). It's unclear
if later changes to the code were only necessary to work
around it.
Change-Id: Iad85af516a7b9f9c0269ff9652ed15ee81700057
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change adds details about the memory map windows to translate
addresses between SPI flash space and host address space to coreboot
tables. This is useful for payloads to setup the translation using the
decode windows already known to coreboot. Until now, there was a
single decode window at the top of 4G used by all x86
platforms. However, going forward, platforms might support more decode
windows and hence in order to avoid duplication in payloads this
information is filled in coreboot tables.
`lb_spi_flash()` is updated to fill in the details about these windows
by making a call to `spi_flash_get_mmap_windows()` which is
implemented by the driver providing the boot media mapping device.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48185
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide get_mmu_ranges() for ARM64 to let payloads could get
MMU ranges for all used memory regions.
BUG=b:171858277
TEST=Build in x86, arm, arm64.
emerge-zork libpayload depthcharge
emerge-nyan libpayload depthcharge
emerge-asurada libpayload depthcharge
Signed-off-by: Meng-Huan Yu <menghuan@google.com>
Change-Id: I39b24aefc9dbe530169b272e839d0e1e7c697742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This turns on the compiler's printf style format string checker.
BUG=b:167517417
TEST=enabled all USB controllers on volteer and fixed resulting
compiler errors when USB_DEBUG is enabled.
Change-Id: Ic94ebcbafdde8a5f79278b5635111b99af40f892
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes format string mismatch errors in the USB subsystem found by
the compiler's format string checker.
BUG=b:167517417
TEST=enabled all USB controllers on volteer and fixed resulting
compiler errors when USB_DEBUG is enabled.
Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The current timeout of 500ms is too low. For instance self-test
of the KBC integrated into IT8516E took almost 1s in tests. We
already check for presence of the KBC before the self-test. So
the timeout should only trigger on a hardware defect and we can
leave some margin.
Change-Id: I95f01a4e605a9c7deb894a71e102c3a881759bb1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Jianjun Wang