Commit graph

5 commits

Author SHA1 Message Date
Andrey Petrov
1ba068550d soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usable
coreboot writes RDSP at 0xf0000. Since depthcharge wipes usable
memory regions before starting, kernel can't find RDSP.

Change-Id: I584bd5d24248cf38f46342615cf3b0252a821b2a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:11:11 +02:00
Martin Roth
ebabfadcec soc/intel: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-14 16:54:33 +02:00
Andrey Petrov
28c78abaf7 soc/intel/apollolake: Reserve IMRs (Isolated Memory Regions)
Certain security features on the platform use IMRs. Unfortunately
this memory is unusable for OS or firware. This patch marks IMR
regions as unusable.

Change-Id: I4803c41c699a9cb3349de2b7e0910a0a37cf8e59
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-13 16:08:09 +02:00
Andrey Petrov
15c736be05 soc/intel/apollolake: Fix MMIO reserved ranges calculation
mmio_resource() takes memory address in kilobytes. This patch
adds resources properly.

Change-Id: Id78dcecf05ad5b2c84e5bb5445ae3a4e4ec9d419
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14203
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-01 18:24:20 +02:00
Andrey Petrov
a2176d8ef6 soc/apollolake: Add memory and reserve MMIO resources
This adds most important MMIO reserved memory resources,
real DRAM memory resources, and some DRAM resources that
can not be used as RAM for whatever reason.

Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13360
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-10 23:11:10 +01:00