- Remove functions that are only called in one place.
- Add warning if user doesn't supply a platform, since that can lead to
dumps/layouts that do not include all IFD regions without the user
even reliazing it.
- Inform the User if IFD or Flashmap is not found.
- Inform the User if there is not a single match between FMAP and IFD
region
- Avoid printing usage if not specifically asked by the user.
It tends to obfuscate the original error message.
- Keep indentation consistent throughout the file.
- Remove typedefs (coreboot coding style)
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7bbce63ecb2e920530394766f58b5ea6f72852e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Type 0x5d (MPIO Firmware) was mistakenly placed to PSP Level 1 directory.
It should be in Level 2 PSP directory instead.
Change-Id: Ic5ea00859f1055e0c91600c5f941c5d3acca36e2
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Use the inst field when adding entries to the psp tables. Otherwise,
entries that differ by the inst field will appear as duplicates with an
inst of 0.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I4a84a0730976f4c65902b5c24ed13e21e95b03bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
It is similar to PSP combo.
Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
If combo is used, fill the EFS header with address of COMBO header.
If not, fill with address of PSP header.
The old code fills with PSP headers all the time.
Change-Id: I0057165aea553d9dc8e4e719e2804557229a0002
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66855
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There will be a loop to set up the combo layout. The combo header only
needs to be created once. This change is actually to move the creation
of combo header outside of the loop.
Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is easier to understand what these statements are about.
Change-Id: Ib02c68c9f2ea84020b12682c41fb1a6f8f93d725
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66852
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In a recent coreboot leadership meeting, the decision was made to allow
(but not require) braces around single line statements if the author
wishes to put them in.
This patch removes the checks for single line statement blocks, while
still checking for other issues in braces.
Just because they're allowed now, please do not reformat the entire
codebase to add them. coreboot has a policy of not making widespread
changes to the entire codebase unless something actually violates the
style guidelines.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I137b10889ec880959c4c1b035dc54bf8ebf32488
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73515
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the last slash '/' from directories in excludelist, so that they
will be correctly filtered by grep.
Fixes:
grep: util/goswid: Is a directory
grep: util/nvidia/cbootimage: Is a directory
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I90cc2cff9a98bbd0af344156332b970bfd6430b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
To support 32M flash, the non-vboot also need to split amdfw. Just as
the deleted comment says, we need this feature now.
This is one of series of patches to support 32/64M flash.
BUG=b:255374782
Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
To support 32M flash, the non-vboot also need to split amdfw.
The amdfw.rom is the default filename added to CBFS.
Keep the default filename and then we don't have to change all the
CBFS definition.
This is one of series of patches to support 32/64M flash.
BUG=b:255374782
Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add a new flag "--utc" to allow the user to choose if
elogtool should print timestamps in Local Time or in UTC.
It is useful for generating automated crash reports
including all system logs when users are located in
various regions (timezones).
Add information about timezone to timestamps printed
on the console.
Signed-off-by: Wojciech Macek <wmacek@google.com>
Change-Id: I30ba0e17c67ab4078e3a7137ece69009a63d68fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
This filling does not need to be done separately.
Change-Id: I53051349923dce40f4fc3f747ab41a93a3798823
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
A few references to "--combo-capable" were left after commit 4bfb36ed68
Change-Id: I6f425db2a8b86d7ad928baee6bc7b07e5190ba37
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73281
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the EFS data is being packed, the pointer should be at EFS
header.
After that, it should be at body location.
TEST=binary identical test on amd/birman amd/chausie amd/majolica
amd/gardenia pcengines/apu2 amd/mandolin
Change-Id: Ia81e2bdf9feb02971723f39e7f223b5055807cd8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
We need to considering the case the EFS header is given as a relative
address and the other, body location, is given as an absolute one. So
we convert both of them to relative and check the validation.
For relative address case, the location should be between
0 and data size.
Change-Id: I7898bfbca02f5eb1c0fb7c456dc1935bddf685b1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
If ctx.address_mode is "physical", it will keep as "physical".
If ctx.address_mode is "relative to table", it will be changed as
"relative to BIOS".
Because the "current table" is the whole flash, the code worked well.
TEST=Binary identical test on amd/birman amd/chausie amd/majolica
amd/gardenia pcengines/apu2 amd/mandolin
Change-Id: I9acb54cc5de149d8a705bb05bf351c44b7d3ced1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Changing the pointer outside the function is not allowed.
Check if it overflows everytime it changes.
TEST=Binary identical on amd/birman amd/chausie amd/majolica
amd/gardenia pcengines/apu2 amd/mandolin
Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Now we use ctx.rom. Remove the wrong statement releasing null
pointer.
Change-Id: I134335ed741dc067e232621106f2057e50ba6a1a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
It is not more necessary to patch binutils, we can
pass an argument during build time to not build docs.
Regenerate binutils-2.37_no-makeinfo.patch.
Change-Id: If600f0bb46db5f84956940683a7adc83eaca01e5
Signed-off-by: Elias Souza <eliascontato@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73115
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add support for LP5X 8533Mbps in SPD tool.
BUG=b:263189532
TEST=None
Change-Id: I72b02514f68647dda996822f910db8bc93f61ca4
Signed-off-by: Kyle Lin <kylelinck@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marx Wang <marx.wang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
While the work on updating GCC to version 12 is still WIP, update it
to the latest minor release 11.3.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I8810bbb238b01985774ff8da1e246ab1b192e663
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70221
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
We can not use 'boolean' since commit 53ea1d44 "util/kconfig: Uprev to Linux 5.13's kconfig".
This also reduce difference with upstream.
Change-Id: Iff9fbde46784547c07726816d2fdd71967e0595e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
- Make variables for the release name and the tarballs instead of
writing them out every time.
- Skip some more unnecessary files when creating the tarballs.
- Remove unnecessary check for the commit ID. It's now a required field.
- Correctly get and save the time of the last release for use in
creating the tarballs.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I56cd5e2dcf01ee55e5d45e837db2f89904b06ddd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Since it actually depends on the SoC type whether the old PSP
directory table pointer or the new comboable PSP directory table
pointer is used in EFS, get this information from the SoC ID instead
of passing the comboable flag for the SoCs that need to use the new
comboable PSP directory table pointer.
TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia
Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This corrects the word "echi2" to "ehci2".
Change-Id: Id8911de147538f4614627cfca449bad528ab6780
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The fw.cfg should combine the SOC name.
This is for future combo feature. Each entry in combo has its own
fw.cfg.
The soc_id in struct cb_config can only be available after the fw.cfg
is processed.
Some functions which take soc_id as a parameter can be simplified.
3/5 (and the key one with same change ID)
of split changes of https://review.coreboot.org/c/coreboot/+/58552/28
Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Allow user to pass the output dir for the extracted blobs as the 2nd
argument to the script; if not provided, fall back to the existing
default.
Change-Id: I0f120b69e0b6d14c2763b9a3b2a622e77c4fe0d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Save the soc_id into a global struct.
Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need to put soc name to fw.cfg for future combo feature.
We skip for now when SOC_NAME is found.
1/5
of split changes https://review.coreboot.org/c/coreboot/+/58552/28
Change-Id: I2b8d7154d22db13675ff57b6abe61c747604c524
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
For Carrizo, the soc name was set as UNKNOWN.
The change is supposed to be binary unmodified, except the SPI
settings. According to the spec, the Stoneyridge and Carrizo have the
same definition of SPI setting in EFS.
Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
When the BIOS size is more than 32M, the physical address of EFS
header will be complicated, like 0xfe020000 or 0xfc020000. So we make
it simpler to allow to use relative address.
This CL works with https://review.coreboot.org/c/coreboot/+/69852
TEST=Result image is binary same on
amd/birman amd/majolica amd/gardina amd/mandolin
Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This is currently killing the jenkins builds. This patch allows it to
be disabled until the reason is found.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I16dba80a88953aa95f7f647ba12b2ec3297ab81f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The address mode is an internal mode which AMD FWs use. Regular
developers don't have to know that. Just report the relative address
every time. For the cases head and body are split, the address of body
is also reported.
Change-Id: I77d9aac0b3d996363341c1d2dae049ec344b39aa
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This change adds 2 command line parameters, --skip_set and --skip_unset
that allows abuild to skip boards with particular Kconfig values either
set or not set.
Note that it only works on BOOL type variables.
This can be set on the abuild command line, or the JENKINS_ABUILD_OPT=
variable on the make command line.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I43336484cf25f83065ec7facf45c123d831024b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Flashrom needs libgpiod-dev to build the new bitbanging programmer
driver for Linux libgpiod.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I88f7e11fab115487cc44d4b89b3eab4745ad058d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
And make less levels of indentations in the code.
Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This allows the user to pass one or more arguments through the testsoc
script to abuild.
Example:
testsoc -K SOC_AMD_CEZANNE -a "--skip_unset BOARD_GOOGLE_NIPPERKIN"
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72766
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On family 15h and 16h processors with PSP, the PSP firmware type 0x5f
corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this
corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to
clarify this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
For the PHX, it uses subprog 0.
For the PHX2, it uses subprog 1.
Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The testsoc script was pulling in odd results when the -K option matched
options in sources, Makefiles, and device trees. Adding another grep to
limit the list to just Kconfig matches ensures that only actual
mainboards are built.
TEST="./util/testsoc -K PICASSO" no longer tries to build mainboard "0"
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3860df4520a5594fb9c1a06e75487520b7d5d275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72655
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support logging events for when we show early signs
of life to the user during CSE FW syncs and MRC trainings add
support for the ELOG_TYPE_FW_EARLY_SOL type.
BUG=b:266113626
TEST=verify event shows in eventlog CSE sync/MRC training
Change-Id: I3913cb8501de9a2605266cf9988a7195576cb91d
Signed-off-by: Tarun Tuli <tarun.tuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71296
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Maximilian Brune