Commit graph

8 commits

Author SHA1 Message Date
Elyes HAOUAS
777ea897e8 src/arch: Capitalize CPU, RAM and ROM
Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15953
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 18:35:09 +02:00
Aaron Durbin
e0969aec25 x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.

BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
     libpayload.

Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-19 19:50:10 +01:00
Aaron Durbin
f6ada1c307 lib/coreboot_table: add function to allow arch code to add records
Add lb_arch_add_records() to allow the architecture code to
generically hook into the coreboot table generation.

BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed lb_arch_add_records() is
     called when a strong symbol is provided.

Change-Id: I7c69c0ff0801392bbcf5aef586a48388b624afd4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13669
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-19 19:21:15 +01:00
Martin Roth
e369010ab8 arch/x86: Indent using tabs not spaces
No functional changes - just whitespace fixes.
Signed-off-by: Martin Roth <martinroth@google.com>

Change-Id: I8ffa87240bcbd3d657ed9dc619b5e5bf9de734d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12853
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 00:36:48 +01:00
Martin Roth
9df9e93914 arch/x86: add missing license headers
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.

memmove.c came from the linux kernel, so also gets the standard
coreboot v2 license header, but gets the added attribution that it
was derived from the linux kernel.  Unlike many coreboot files,
this file may not be re-licensed as GPL V3.

Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12916
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 23:37:06 +01:00
Damien Zammit
149c4c5d01 x86/smm: Initialize SMM on some CPUs one-by-one
We currently race in SMM init on Atom 230 (and potentially
other CPUs). At least on the 230, this leads to a hang on
RSM, likely because both hyperthreads mess around with
SMBASE and other SMM state variables in parallel without
coordination. The same behaviour occurs with Atom D5xx.

Change it so first APs are spun up and sent to sleep, then
BSP initializes SMM, then every CPU, one after another.

Only do this when SERIALIZE_SMM_INITIALIZATION is set.
Set the flag for Atom CPUs.

Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/6311
Tested-by: build bot (Jenkins)
Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-02 00:38:45 +01:00
Aaron Durbin
037581542b symbols: add '_' to pci_drivers and cpu_drivers symbols
In order to prepare for more unification of the linker
scripts prefix pci_drivers, epci_drivers, cpu_drivers, and
ecpu_drivers with an underscore.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built different boards includes ones w/ and w/o relocatable
     ramstage.

Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11506
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-05 15:36:23 +00:00
Stefan Reinauer
6cb3a59fd5 x86: flatten hierarchy
It never made sense to have bootblock_* in init, but
pirq_routing.c in boot, and some ld scripts on the main
level while others live in subdirectories.

This patch flattens the directory hierarchy and makes
x86 more similar to the other architectures.

Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10901
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-13 21:04:56 +02:00
Renamed from src/arch/x86/lib/cpu.c (Browse further)