Thatcher features: Family 15 trinity FP2. Hudson.
close to Parmer.
This board and parmer both need to revert the change
http://review.coreboot.org/#/c/1359/, and add thatcher's own
chip.h,otherwise the mainboard_enable can not be called.
Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1382
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Before (data flag ignored -> broken):
66 DATA:
e944f1 JMP 1ff6
After (fixed):
66 DATA:
e944f1ffff JMP 00001ff8
This subtle difference in the length of decoded instruction meant
that the VBE call jumped to the routine setting AX=0x14F (VBE Failed)
instead of the routine that set AX=0x4F (VBE success).
The ability to run the same code in vm86 significantly aided the
debugging of this issue. Those X.org developers who would like to drop
vm86 better take special care towards _all_ vesa bugs, as those will
expose further issues.
Imported from:
http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=cc2c73ddcb4370a7c3ad439cda4da825156c26c9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Id08ead9b17468cf19ede45508e5dcc50e45b5acf
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Tested-by: Luc Verhaegen <libv@skynet.be>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-on: http://review.coreboot.org/1365
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
cc2c73ddcb4370a7c3ad439cda4da825156c26c9's three-cent titanium tax
doesn't go too far enough. Fix the rest of the call and jmp
instructions to handle the data prefix correctly.
Reference: Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 2A: Instruction Set Reference, A-M
http://www.intel.com/Assets/PDF/manual/253666.pdf
Imported from:
http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=bb18f277156c08be028a6e12d8987fb1593e9168
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I83e6245d9748ee86722cfb7d8ac65258c35c013c
Reviewed-by: Julien Cristau <jcristau@debian.org>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-on: http://review.coreboot.org/1366
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This patch validates the previous "drop uma_memory_base" patches;
there are no more references to uma_memory_base when GFXUMA is not
selected.
Change-Id: I735b5e765b0c5cb4af1b4a7470cfe1af2bda7d38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1385
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
UMA region can be determined at any time after the amount
of RAM is known and before the uma_resource() call.
Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1379
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Without GFXUMA, variables were not referenced anywhere.
Fail builds on Family10 if GFXUMA is selected, because the northbridge
code does not set UMA base or size.
Change-Id: I15b91cf6241e9a890398eed03824b753828a0a51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1247
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The code in rs690 or rs780 is always used with K8 or AMDFAM10
northbridge. Without GFXUMA, both of these set the same static value
indirectly using the variable uma_memory_base.
Make the register setting with immediate value, to remove the obscure
use of variable uma_memory_base.
Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1246
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
I dont known if missed something, but why an extra 0x100 was added to limit?
My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which
is higher than TOM.
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-000000005e13efff: RAM
3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES
4. 000000005f000000-000000007effffff: RESERVED
5. 000000007f000000-000000007fffffff: RAM
6. 00000000a0000000-00000000afffffff: RESERVED
Ronald G. Minnich:
I think someone who wrote the code was trying to round up the
next 0x100 boundary and did it incorrectly.
Here is code that would do it correctly:
limitk = ((resource_t)((d.mask + 0x00000ff) & 0x1fffff00)) << 9 ;
Zheng:
Plus 0xFF is correct, but the d.mask take bit 0 as enable it.
This bit should be clear when we try to calculate the limitk.
Change-Id: I3848ed5f23001e5bd61a19833650fe13df26eef3
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1265
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Use of uma_resource() in northbridge code created a memory
resource marked as reserved. Such resources are removed
from system memory in write_coreboot_table().
Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1238
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
With SandyBridge northbridge code, uma_memory_size was reset to
zero before variable MTRRs were set. This means MTRR setup routine
did not previously create a un-cacheable hole for uma.
Keep the behaviour that way, mmio_resource() has a prerequisuite that
the new region does not overlap with any cacheable ram_resource().
The result is not optimal setup in the number of used MTRRs, but
continue with this approach until MTRR algorithm is improved.
Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1373
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reserved memory resources will get removed from memory table at
the end of write_coreboot_table(),
Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1372
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This reverts commit 042c1461fb.
It turned out that sending IPIs via broadcast doesn't work on
Sandybridge. We tried to come up with a solution, but didn't
found any so far. So revert the code for now until we have
a working solution.
Change-Id: I7dd1cba5a4c1e4b0af366b20e8263b1f6f4b9714
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1381
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This reverts commit 78efc4c36c.
The broadcast patch was reverted, so this commit should also
be reverted. The reason for reverting the broadcast patch:
It turned out that sending IPIs via broadcast doesn't work on
Sandybridge. We tried to come up with a solution, but didn't
found any so far. So revert the code for now until we have
a working solution.
Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1380
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Some usb debug devices don't respond fast enough. The linux kernel
(which uses almost the same usbdebug code) added a bit more
retry code, so let's copy that. Even if it might look stupid,
i pass the DBG_LOOPS argument through all functions to keep
the code at least a bit in sync with the linux kernel code.
Change-Id: I7c4b63b8bf1d2270fd6b8c8aa835e2cb324820bd
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1375
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Compilation fails with set_debug_port undeclared in ramstage and
smm code. Fix that by adding usb_debug.c to the appropriate stages.
Change-Id: I2a037d3c5fab76ae6ea65c3a7f4d4e7561bb6d34
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1376
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
MRC messes with USB devices, so we have to reinitialize
USB debug after MRC has finished.
Change-Id: I45c0a687cebd69d0a31235bb870f8c455f42d4f2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1377
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit 2d42b34003 changed the
variable MTRR setup and removed compensation of uma_memory_size in
the cacheable memory resources.
Since the cacheable region size was no longer divisible by a large
power of 2, like 256 MB, this caused excessive use of MTRRs.
As first symptoms, slow boot with grub and poor user response.
As a solution, register the actual top of low ram with ram_resource(),
and do not subtract the UMA/TSEG regions from it.
TSEG may require further work as the original did not appear exactly
right to begin with. To have UMA as un-cacheable, use uma_resource().
Change-Id: I4ca99b5c2ca4e474296590b3d0c6ef5d09550d80
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1239
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
This instruction is being used in some debug VBIOSes. This implementation
doesn't even try to be accurate. Instead, it just increments the counter by a
fixed amount every time an rdtsc instruction in encountered, to avoid divides
by zero.
Imported from:
http://cgit.freedesktop.org/xorg/xserver/commit/?id=c4b7e9d1c16797c3e4b1200b40aceab5696a7fb8
Change-Id: I8fba1a060c57ccb7bbd44aa321dd349bc56bf574
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
No need for the test, tomk is at most 1GB on these chipsets.
Even if there was no room, adjusting the memory resource would not
not divert accesses in the hardware from DRAM to PCI.
Change-Id: I2213b8d9d2e6ab8da8fd3e8081cc62bb05b6b316
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1369
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
No need for the test, tomk is top of low memory and always below 4GB.
Change-Id: Ifc8f29268b761aa9b07b578673236a673f0c70b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1368
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Hide some details of the resource allocator from rest of the world.
These should come in handy when fixing some aspects of MTRR setup.
Change-Id: I8acad98f25e56cd8bae64fb52539d81ce94f9c73
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1367
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Old rev (1.6.6, in my case) git-describe doesn't take the --dirty and says error.
Remove the --dirty at second try.
Change-Id: Id6c6f9889ab20fb7c2b238f8c0bbe20134757369
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1261
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
mainboard_config never worked right, at least not since we've had sconfig.
Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that
tried to use it anyways.
Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1359
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Our driver infrastructure became more flexible recently.
Make use of it.
These are the low hanging fruits (files with 5 device
variants or more), but there are still lots of files
with less potential for deduplication.
Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
We used a hard coded value for some reason. Don't do that, but use CMOS
instead.
Modelled after http://review.coreboot.org/#/c/443 to get bd82x6x in
sync.
Change-Id: I36d715310157b9f9074f2a1c80710f85833020b4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1324
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.
These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.
Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)
Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Otherwise there is a flurry of TDP changes with suspend/resume
as the kernel powers devices off on suspend and brings them
back online in resume.
This also adds a mutex around the TDP operations since it is
split across two methods and can't just rely on being Serialized.
Change-Id: I7757d3ddad34ac985a9c8ce2fc202e2b2dcb2527
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Recent changes in EC/Vboot/U-boot have completely broken
the logging of developer and recovery modes.
Recovery mode may not be in VBNV, so if that is zero and
yet we are in recovery mode then assume it is there because
the button/key was pressed.
Since there may not be any actual developer mode switch
we look if option rom is loaded and the system is not
in recovery mode and consider that as developer mode.
Change-Id: I70104877b24de477217e1ff5b3a019aef22343ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1346
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This will log if the ME is disabled or has an error.
1) disable ME via EC console: gpioset PCH_HDA_SDO 1
2) boot the device
3) read eventlog with "mosys eventlog list"
71 | 2012-07-13 10:10:55 | Management Engine | Disabled
Change-Id: I9f6ee452d2aea76e6a5ea2cd50a50ff36245692a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1345
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The required power MSRs are mirrored in MCHBAR so
it is possible to configure TDP at runtime via ASL.
This adds the required fields and a set of methods to
configure "TDP down" and "TDP nominal". It explicitly
does not support "TDP up" at the moment.
PSSS: method is added to assist in searching the _PSS
table for the appropriate entry that corresponds to the
desired max non-turbo ratio.
STND: Set TDP Down from Nominal. This will limit CPU to
the TDP down configuration by sequencing the required
changes in the right order.
STDN: Set TDP Nominal from Down. This will set the CPU
back to nominal configuration by sequencing the required
changes in the correct (reverse) order.
This does not introduce any functional changes and must
be paired with additional changes to be useful.
The current configured TDP can be checked to see that
the transition to/from a desired level is successful.
> mmio_read8 0xfed15f50
0x00 # TDP-Nominal
> mmio_read8 0xfed15f50
0x01 # TDP-Down
Change-Id: I31a2f30cc9d134cc5eee980ae9288ae45e71c6e6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1344
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The default TCC activation offset is 0, which means TCC
activation starts at Tj_max. For devices with limited
cooling ability it may be desired to lower TCC activation.
This adds an option that can be declared in the devicetree
to set the TCC activation to a non-zero value.
Enable tcc_offset=15 in devicetree.cb and build/boot
the BIOS and check that the value is set in the MSR:
> and $(shr $(rdmsr 0 0x1a2) 24) 0xf
0xf
Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1343
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Split this behavior out from PNOT() so the OS can
update _PPC limit without re-reading C-state tables.
Change-Id: I81b9111a4866f6b9916f74ac57a3caefaa77c565
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1342
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The existing NVS variable for PPCM will be used to
select a dynamic max P-state.
By itself this does not change existing behavior because
the NVS PPCM variable is initialized to zero.
PPCM can be tested by building and booting a modified BIOS
that sets gnvs->ppcm to a value greater than 1 and checking
from the OS that the P-state is limited to that value.
Change-Id: Ia7b3bbc6b84c1aa42349bb236abee5cc92486561
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1341
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This will allow various teams to select which thermal sensor
will control the thermal zones.
Also add a method to notify the thermalzones of a change
so these threshold/sensor methods take effect.
Needs a modified BIOS that uses the NVS TMPS value in
the thermalzone to read a different sensor.
Then, use a kernel driver that contains the following:
/* Adjust temperature sensor id to 2 */
union acpi_object param;
struct acpi_object_list input;
param.type = ACPI_TYPE_INTEGER
param.integer.value = 2
input.count = 1;
input.pointer = ¶m;
acpi_evaluate_object(NULL, "\\TMPU", &input, NULL);
And ensure that the temperature sensor that is being
monitored switches to ID 2.
Change-Id: I6319741358ba31eb8a3dc635d64f3f0acf683386
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1340
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ME device was being sent EOP and the PCI device hidden during
coreboot so it was not available in the SMI finalize step.
This also flips the PCI vendor/device dword around for the match.
Boot on Panther Point with serial and SMI debugging enabled and see
that ME EOP message is sent and the device is hidden at end of
U-boot and before the kernel loads.
Finalizing Coreboot
SMI# #0
ME: mkhi_end_of_post
ME: END OF POST message successful (0)
PM1_STS: TMROF
PM1_EN: 120
Starting kernel ...
Change-Id: I230038c62c50db2a1c94078c0a2a67bdc232440e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1338
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The LPC bus normally allocates the range for legacy devices,
0-0x1000. Some devices on LPC are above that range and need to
be accounted for. Check the decode range settings for addresses
> 0x1000 and reserve them.
Change-Id: Idba800d7cee3185296f29dd237ba306f3de8de55
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1337
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Events are logged for SMIs that trigger ACPI sleeps state
entry and when the power button press triggers an SMI such
as at the developer/recovery screens.
Generate ACPI sleep state events and power button
events and verify they show up in the log:
153 | 2012-06-23 17:12:59 | ACPI Enter | S5
184 | 2012-06-23 17:15:50 | ACPI Enter | S3
216 | 2012-06-23 17:28:58 | Power Button
Change-Id: Iba134d619780e459bce189d36d57844997ffb009
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1320
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Unfortunately the drive strength values are very much board
specific and different between mobile and desktop so we don't
try to do any fancy detection here but let it be specified
directly in the devicetree.
Change-Id: I66674bff0de04ecd088fb09afad1cf801a374df2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1347
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to support the GSMI interface the SMI handler needs
to find and use the state save area from the same CPU that
initiated the SMI. In this case it is a synchronous SMI
resulting form an IO write to port 0xB2.
To find the right CPU state save area iterate over the region
until the "IO Misc Info" field reports the expected value and
then proceed to use that state save area.
This is needed because the coreboot SMI handler only executes on
one core, and that core is non-deterministic. It is likely that
the core executing the C SMM handler is not the same one that
actually did the IO write to 0xB2 and generated the SMI.
The GSMI parameter buffer is passed as a pointer to EBX in the
tate save area, and the GSMI command is extracted from EAX before
it is used as the return value.
This interface is tested by enabling CONFIG_GOOGLE_GSMI in the
kernel and generating events and verifying that they end up
in the event log.
159 | 2012-06-23 16:22:45 | Kernl Event | Clean Shutdown
184 | 2012-06-23 17:14:05 | Kernl Event | Oops
185 | 2012-06-23 17:14:05 | Kernl Event | Panic
Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1317
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Read event routine didn't get the correct BIOS callout. So it could not get
the heap address. Then it would creat many warning in serial port.
Change-Id: Ia35601bda1579c7f726ed767d7be78713ac185d2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The board has a marvell NIC, but the driver to disable NIC BIOS was adapted
from a Realtek 8168 driver. Rename to reflect the change.
Also hook up as driver, so coreboot can actually find it.
Change-Id: Ibdfd6074eb28ba537d68552a3346b06493cef2a6
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
One copy was slightly different, but all the differences were commented out
Change-Id: I3cc7b5621c681a1eb286f9b16ef3ebdce03abb6b
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1356
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
EHCI debug allows to send message with 8 bytes length, but
we're only sending one byte in each transaction. Buffer up
to 8 bytes to speed up debug output.
Change-Id: I9dbb406833c4966c3afbd610e1b13a8fa3d62f39
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1357
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
On SandyBridge systems configured to work with Panther Point the CPU
would wrongly be described as IvyBridge. Fix this issue and drop an
unneeded Kconfig variable at the same time.
Change-Id: I501a4fa00613e589cd315cfee61b2f9561dfcb4d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1335
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
zbao