Opens a binary file to extract DDR SPDs using known bits.
At the moment only DDR4 SPDs are supported.
Dumps the found SPDs into the current folder, as either
binary or hex encoded file.
Works with python2 and python3.
Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch changes a few more Kconfig linter warnings to errors that
currently do not show up in the tree and that seem unlikely to become
false positive in the future. One instance of duplicated code that
essentially checks for the same thing was consolidated.
It also adds a new test for references to boolean Kconfig options that
do not use the CONFIG() wrapper macro. It's a little flaky (e.g. hard to
handle multi-line comments), but it should be helpful the majority of
the time as a warning in a Jenkins comment.
Change-Id: I975ee77d392ed426f76f7671d9b6ef9441656e6a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The last part of the file has not been modified much.
Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30969
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the values are hardcoded, we might as well hardcode values that
make sense.
Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 626ba097a2.
This change was submitted under the incorrect assumption that there was
agreement on a coding style change. There wasn't, so while the issue is
under discussion we should revert to the previous status quo.
Making clang-format honor the line length is a separate issue from
changing the line length, and can be reuploaded as a separate CL.
Change-Id: I433c82c95a897b3113cace3668cc8ce0f1ab75bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Values from
- Intel doc 337347 rev4
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not
accessible. Using a static value instead. 0xfd000000 is a common value
chosen by coreboot and non-coreboot firmware.
Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A side effect of the change 8e0dca05
"util/amdfwtool: Add generic image copy function"
was to treat a read operation of zero bytes as a failure. Some
implementations exist that use zero length files as a means of
removing functionality. This causes amdfwtool to exit with an
error.
Put the zero length capability back in, and generate the requested
table entry with a length field of 0x0.
TEST=Boot google/grunt, inspect PSP directory table
BUG=b:128507639
Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This symbol was removed in
a6be58fece ("nb/intel/sandybridge: Remove the C native graphic init")
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: I87801552e1c37162897949ec0db3904f850f0bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe
root ports. Put the latter on sandybridge.go instead, and add missing
IDs.
Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the Kconfig linter to support the new CONFIG() macro
in the same manner that IS_ENABLED() was previously supported. It will
be flagged when it is used on non-bool Kconfigs or used with #ifdef, and
it is supported for checking used Kconfigs. Remaining uses of
IS_ENABLED() are flagged with a deprecation warning.
Change-Id: I171ea8bc8e2d22abab7fc4d87ff4cf8aad21084f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31776
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the older chipsets that are known not to have ME at all
were removed for some reason, add them back in.
Also some newer chipsets/ME models were missing, add them in.
Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Complete the removal of the fanless command line options. The only soc
using them has been converted to use the subprogram option instead.
TEST=Verify amdfw.rom is unchanged before and after the conversion
BUG=b:126691068
Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Separate the type field for the PSP directory table to better match the
AMD Platform Security Processor BIOS Architecture Guide (order #55758,
NDA only). Instead of a 32-bit type, change to an 8-bit value and an
8-bit subprogram field to allow for a more generic application across
family/model products.
This patch also eliminates the "fanless" types, previously added for
stoneyridge, and converts the --smufnfirmware and --smufnfirmware2
arguments to use a subprogram value of 1.
Subsequent patches will change the stoneyridge makefile to use the
new option, and eliminate the fanless arguments.
TEST=Boot google/grunt, confirm no difference in amdfw.rom file.
BUG=b:126691068
Change-Id: If8f33000c31cba21f286f54459de185c21e46268
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace variables and function arguments with a context that may be
maintained and passed. Add macros to clarify the pointer math. Add
functions to generate tables instead of relying on correct ordering
and math. Use defined sizes for tables instead of arbitrary additions
to an index.
TEST=Verify no difference in amdfw.rom for google/grunt before and
after, and verify a grunt build with PSP_COMBO=1 runs.
Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Consolidate the code that opens, stats, copies, and closes the
individual files into a single function.
TEST=Verify no difference in amdfw.rom for google/grunt before
and after the patch is applied
Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Rename psp_fill_head() and call it with the cookie to populate the
header. The combo header and PSP directory header are similar and
should be calculated the same way.
Change-Id: I7e634542de65576addadbe683596cbe572de3dcd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed. Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.
This patch is part 2 of 2 to reduce the number of command-line options
to amdfwtool. Part 1 added the --combo-capable option that helps
put the PSP directory pointer in the correct location. Part 2
removes the duplicated table, the support code, options, and updates
the usage text.
TEST=Build before/after images for grunt, bettong, apu2, and diff
hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO
defined as 1.
BUG=b:126691068
Change-Id: I542a7f5023137f30fbe00533452d4448117df487
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed. Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.
This patch is part 1 of 2 to reduce the number of command-line options
to amdfwtool. Create a new option that is used as an indicator for
which Embedded Firmware offset to use. Part 2 will be added once
makefiles no longer use the duplicated options.
This patch also adds two new options for fanless SMU firmware to be
used instead of the ones that will be removed in part 2.
TEST=Verify no difference in amdfw.rom for google/grunt before
and after the patch is applied
BUG=b:126691068
Change-Id: I249700c6addad1c0ecb495a406ffe7a022dd920b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The fletcher32 algorithm generates a sum over a range of 16-bit
WORDs. Change the function's interface to be more generic,
accepting a more intuitive size in BYTEs. Don't require the
caller to understand the nature of the algorithm and convert to
WORDs prior to calling.
TEST=Verify no difference in amdfw.rom for google/grunt before
and after the patch is applied
Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the use of multiples of DWORDs with structures that
describe the Embedded Firmware Table, and PSP directory
headers & entries.
TEST=Verify no difference in amdfw.rom for google/grunt build
(Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh),
and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but
was not verified.
Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct an oversight in the utility that attempts to match up eligible
PSP directory table entries with blob names passed on the command
line. A 1:1 matchup of items shouldn't be assumed, so the i iterator
shouldn't be used to walk both lists.
This change has no effect on google/grunt (Family 15h Models 70h-7Fh),
but eliminates blank entries of all FF's on builds of amd/bettong
(F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries
also affects the checksum accordingly.
TEST=Build before/after images for grunt, bettong, apu2, and diff
hexdumps of the amdfw.rom files
Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The __pci_driver and __cpu_driver uses variable length arrays which are
constructed by the linker at build-time.
The linker always place the structs at 16-byte boundary, as per
"System V ABI". That's not a problem on x86, as the struct is exactly
16 Bytes in size. On other platforms, like x86_64 it breaks, because the
default data alignment isn't SysV compatible.
Set -malign-data=abi to make x86_64 gcc use the SysV psABI.
Fixes broken __pci_driver and __cpu_driver on x86_64.
Change-Id: I2491d47ed03dcfd8db110dfb181b2c5281449591
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on not publicly available IT8613E Preliminary Specification V0.3.
Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is a great check, but unfortunately it's currently not effective
because most uses of IS_ENABLED() do not have whitespace in front of
them (they're mostly used as part of an if (IS_ENABLED(...)) condition).
This patch makes the linter a little more generous in what it considers
in scope to avoid these false negatives in the future.
Change-Id: I2296410c73cd6e918465c90db33e782936bec0f9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When updating firmware, it is very often that we may want to preserve
few sections, for example vital product data (VPD) including serial
number, calibration data and cache. A firmware updater has to hard-code
the section names that need to be preserved and is hard to maintain.
A better approach is to specify that in FMAP area flags (the `area_flag`
field) using FMAP_AREA_PRESERVE. With this patchset, a FMD parser flag
"PRESERVE" is introduced and will be converted to FMAP_AREA_PRESERVE
when generating FMAP data (by fmap_from_fmd.c).
For example, The FMD statement:
RO_VPD(PRESERVE)@0x0 16k
will generate an FMAP firmware section that:
area_name = "RO_VPD"
area_offset = 0
area_size = 16384
area_flags = FMAP_AREA_PRESERVE
BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices
Manually added 'PRESERVE' to some FMD files, and verify (by running
fmap.py) the output coreboot.rom has FMAP_AREA_PRESERVE set
Change-Id: I51e7d31029b98868a1cab0d26bf04a14db01b1c0
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The recent toolchain update also updated binutils, which has a new
relocation type, introduced with commit bd7ab16b
(x86-64: Generate branch with PLT32 relocation).
Add support for R_X86_64_PLT32, which is handled as R_X86_64_PC32.
Add comment explaining the situation.
Fixes build error on x86_64.
Change-Id: I81350d2728c20ac72cc865e7ba92319858352632
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The idea of "annotation" for firmware sections was pretty flexible, but
in future we will want multiple attributes applied to same area. For
example, indicate the section must be preserved when updating firmware
so serial number or MAC address can be preserved.
The solution here is to extend annotation so it can take multiple
identifiers (flags) in a row. For example, to declare a 64KB COREBOOT
section as CBFS using annotation:
COREBOOT(CBFS)@0x0 64k
If there's a new flag "PRESERVE" indicating the section must be
preserved before update, we can declare it following CBFS flag:
COREBOOT(CBFS PRESERVE)@0x0 64k
The flags are directly parsed in fmd_parser, and stored in an union
flashmap_flags. Output modules can choose to ignore or process the
flags.
Currently the only supported flag is "CBFS" (for backward compatible
with annotation). There will be more new flags in follow up patches.
BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices
Change-Id: Ie2d99f570e6faff6ed3a4344d6af7526a4515fae
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31706
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
git diff needed to emit diffs without prefix (e.g. a/ and b/) for
clang-format-diff to be able to work.
Also require that the test succeeds, but note that it only runs on
trees whitelisted in $(top)/.clang-format-scope.
Change-Id: I7e9a32eb9281b5cb0b45506a206500fd1d315372
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
80 chars + 2 tabs was the compromise we got to in the last round of
discussion.
Change-Id: I9293a69d1bea900da36501cde512004d0695ad37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Apollo Lake has four GPIO communities each with a single group named
after the physical location of the pads (I guess): North West, North,
West and South West.
Also add some logic to be able to tag the default function of a pad
(with an asterisk before its name). This seems easier to review in the
tables, but we could also encode the number of the default explicitly
instead.
Used Intel documents:
- 334817-001 (datasheet vol. 1)
- 334819-001 (datasheet vol. 3)
Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
When updating firmware, we may need to preserve some sections like VPD,
calibration data, ... etc. The logic can be hard-coded in updater as a
list of known names, but a better solution is to have that directly
declared inside FMAP area flags.
To do that, the first step is to apply the changes in flash map
(http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now
defined and will be set in future with new syntax in FMD parser.
BUG=chromium:936768
TEST=make; boots an x86 image.
Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Relocations for PC relative instructions must not emitted.
As PC64 are unlikely with current code, it never was an issue.
Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31469
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.
The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.
Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Because coreboot's asserts aren't fatal by default, scan-build finds
problems in code that is actually protected by an assert. This
change fixes that and allows us to add asserts to protect
against other failures.
Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.
Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upstream intelmetool is out of date; I suggest I archive it
instead of trying to merge coreboot's changes into it.
However I would like to preserve the licensing of files in the tool
as GPLv2+ where possible instead of GPLv2-only.
Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/31587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
VBT on Intel(R) systems is available via sysfs as
/sys/kernel/debug/dri/0/i915_vbt
However the size of this file reads as 0 causing
intelvbttool to fail. This patch implements incremental reads
with realloc for such cases or whenever the file size is not
available (e.g. reading from stdin).
After this patch is applied, intelvbttool can be used as follows:
sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d
Change-Id: I5d17095a5747550b7115a54a7619b7294a846196
Signed-off-by: Alex Feinman <alexfeinman@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/31531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Allow EC region to be readable by BIOS/CPU so that flashrom
can read it.
BUG=b:123199222
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set,
run firmware_LockedME test.
Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.
Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The coreboot table entry containing the memory entries can have
fields unnaturally aligned in memory. Therefore one needs to perform
an aligned_memcpy() so that it doesn't cause faults on certain
architectures that assume naturally aligned accesses.
BUG=chromium:925961
Change-Id: I28365b204962ac89d65d046076d862b6f9374c06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Manoj Gupta <manojgupta@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now running 1.8.3, with a fix to the theme so search still works, and
a recommonmark version that properly rewrites links to .md files.
Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Version 2 IFD will have flmstr5 as EC region access control, consider it
during descriptor lock/unlock process.
BUG=N/A
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check
flmstr5 value by hexdump the SPI image at offset FMBA+0x90.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8
Reviewed-on: https://review.coreboot.org/c/31111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Cannonlake and Icelake have same read/write region permission settings
with skylake and kabylake, so add it here as well.
BUG=b:123199222
TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the
setting matches 0x0D for read and 0x04 for write.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2
Reviewed-on: https://review.coreboot.org/c/31104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit 48c24ce5ee.
Reason for revert: Commit broke bincfg, and sym_table as a global
variable is less bad than passing it around in function calls.
Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
F81866 detection tested with the iBASE SI-613:
superiotool r4.9-420-g034e5e6
Found Fintek F81866 (vid=0x3419, id=0x1010) at 0x4e
F8196* detection is based on chip IDs provided by iBASE, but untested.
Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39
Signed-off-by: Kyle Stevenson <kstevenson@comqi.com>
Reviewed-on: https://review.coreboot.org/c/31052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts `auto.conf` to an Ada spec file. Write to
$(obj)/cb-config.ads and set the package name to
`CB.Config`.
Change-Id: I97c060d8a613c74a82a18aff9524ad4b01f9df56
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.
UNTESTED: This also updates autoport.
Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On FreeBSD, this test was failing with the error:
"grep: Argument list too long"
- Remove support for testing coreboot not in a git repo. Many of
the other linters already don't support this.
- Use git grep to find offending files, then xargs to print out
the lines.
Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
After merging util/crossgcc: derive date and version from latest commit
(https://review.coreboot.org/c/coreboot/+/30804),
crossgcc build is broken in internal repository due to long version
name;coreboot.org repository is ok because it uses short tag name.
The patch uses "git describe" which is dependent on git tag name.
If tag name is little bit long, it can cause crossgcc build failed.
To avoid this issue, use only short version of hash string
which is fixed length. And it's enough as version string,
because we also use date(CROSSGCC_DATE) together.
TEST=Build crossgcc in both coreboot.org and internal repository
which uses longer tag name and check version string in build log.
Change-Id: I405b2e4e5c05831c25aebf1c73a281adab8ef452
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/31001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file),
some model_206ax code was moved to a common place. However, autoport
was not updated accordingly.
Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30967
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ITE8528 which can be found on the wedge100s.
Most registers are dumped from hardware.
No datasheet is publicy available.
Change-Id: I24b12c0032157a4959336f8b51dadbe7b2e09d66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It was only hooked up for galileo board when using the obsolete
FSP1.1. I don't see how it can be useful...
Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30691
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This way date and version are automatically updated when util/crossgcc
was changed, the version contains the commit ID and we have less churn
on these variables.
Change-Id: I475ba9578a8bb421d7c342d2569d7de7fcf4161d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The old version was unnecessarily complex and allowed one region to
include the other.
Change-Id: Ibf7faf8103c8945b82c3962b5a7b82c3288b871f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30673
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes getting a dump of GPIO registers for these devices.
Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496
Signed-off-by: Shaleen Jain <shaleen@jain.sh>
Reviewed-on: https://review.coreboot.org/c/30604
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on IT8786E-I V0.4.1 datasheet with following remark:
"Please note that the IT8786E-I V0.4.1 is
applicable only to the D version."
Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibf6e290abb01ae1b6b28173a83e88d1d99663ad4
Reviewed-on: https://review.coreboot.org/c/30334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use the `git-format' tool to sanitise coreboot commits such that
they conform to coreboot's coding style.
This fancy piece of machinary allows one to have LibFormat from
Clang to automatically check your commit conforms to coreboot's
coding style, fix any issues automatically and provides you a
diff you may review and apply at your convenience.
N.B. When the `clang-format' binary is not found we issue a warning
that the test was skipped and carry on as usual. Hence, this is
strictly non-enforcing at this current time. You may use it at your
leisure.
Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/c/8037
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update to latest version of iasl:
(From the acpica.org changelogs)
* Fixed a regression introduced in version 20180927 that could cause the
compiler to fault, especially with NamePaths containing one or more
carats (^). Such as: ^^_SB_PCI0
* Added a new remark for the Sleep() operator when the sleep time
operand is larger than one second. This is a very long time for the
ASL/BIOS code and may not be what was intended by the ASL writer.
* Implemented detection of extraneous/redundant uses of the Offset()
operator within a Field Unit list. A remark is now issued for these.
For example, the first two of the Offset() operators below are
extraneous. Because both the compiler and the interpreter track the
offsets automatically, these Offsets simply refer to the current
offset and are unnecessary. Note, when optimization is enabled, the
iASL compiler will in fact remove the redundant Offset operators and
will not emit any AML code for them.
Change-Id: I46a1b1be44328aa2172f4741e9fd0c9b0f4e0430
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28944
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The existing code has several messages that are only printed when the
DEBUG variable is set. These messages are not verbose, and are quite
useful to see how the script is progressing. So, print them
unconditionally.
Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
crosfirmware.sh has dependencies that might not be installed on some
systems. If a dependency is missing, provide a clear message about the
issue and how to resolve it.
Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30549
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's quite useful to know the download progress, as it can take a while
even with a fast connection. For example, the peppy recovery image is
~600 MiB. It also lets the user know that disk space is being filled.
Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30548
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On some systems, such as Debian 9.6, `parted` and `debugfs` are located
in /sbin. Adding /sbin to PATH means that this script can work when run
as a regular user.
Change-Id: I151dba467e2b196f13093334273dae8a05865491
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It's the common name.
Change-Id: Iafa793b961847b2c98282fd035ea96ddf6109012
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
A release may be done from an older commit. It's also not a problem as
commits are stored in the reflog (unlike local changes that the script
guards properly).
Change-Id: I26f1c16c1cdfc9e77e28528b3327ce30c5b82b19
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
It's a separate package on debian, so it may not be installed with perl.
Change-Id: Id82661e1d7e6a025f5b207e3bd61669abc32d328
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Patrick Rudolph