GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
50,930 Commits 1 Branch 29 Tags 216 MiB
Commit Graph

50930 Commits

Author SHA1 Message Date
Elyes Haouas 12149ec0a3 mb/intel/coffeelake_rvp/Makefile.inc: Avoid link to non-existent folder 
Found using 'Wmissing-include-dirs' command option.

Change-Id: I178c849d07e61d7a237629f3be1b52d3b4abb513
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:33:12 +00:00
Elyes Haouas 167b7fcdd9 soc/intel/xeon_sp/nb_acpi.c: Use read{16,32,64}p() 
Change-Id: I89bfbab7850dd9bd29ca2097ee2efce058720ca7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:31:41 +00:00
Elyes Haouas 878a99f554 soc/intel/broadwell/early_init.c: Use {read,write}32p() 
Change-Id: I80b1535b86c7fc05354404d628a0a527a6701498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:31:11 +00:00
Elyes Haouas bc849b5459 soc/intel/baytrail/pmutil.c: Use {read,write}32p() 
Change-Id: I6168be71913d00eb59d38dd4c5cf8f9c7f7ab678
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:30:07 +00:00
Elyes Haouas f12c2b0837 soc/intel/apollolake/pmutil.c: Use {read,wrire}32p() 
Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:29:40 +00:00
Elyes Haouas b988f8aac5 soc/intel/alderlake/bootblock: Use 'false/true' macros 
Change-Id: Ic40f1e935b244f39fa3c1322e5128465c57f5e26
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:28:56 +00:00
Elyes Haouas 347b471901 soc/intel/alderlake/bootblock: Use read32p() 
Change-Id: I3062e5b8a0524059b9695dfd32254c5c53598925
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70578
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:27:12 +00:00
Elyes Haouas 50f651baea soc/mediatek/common: Use write32p() 
Change-Id: I83707071fe1801322dffad7fc89afaef5617f3c7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-12-13 14:26:41 +00:00
Elyes Haouas b433470b02 soc/cavium/cn81xx: Use write{32,64}p() 
Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:26:23 +00:00
Felix Singer eb99f62456 {drivers,superio}/acpi: Replace ShiftRight(a,b) with ASL 2.0 syntax 
Replace `ShiftRight (a, b)` with `a >> b`.

Change-Id: I0751d00186e8dff38e02e7bf7d8ebf5a17514a58
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-12 22:17:43 +00:00
Felix Singer 447c399d35 soc/intel/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntax 
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: I97332e3008ed2e26a75c067baffdabfc7cfcf65f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-12 22:16:44 +00:00
Felix Singer 4bbd807c01 soc/intel/acpi: Replace Subtract(a,b) with ASL 2.0 syntax 
Replace `Subtract (a, b)` with `a - b`.

Change-Id: I77028c17dcd7925a392d56488d34090837d660f2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-12 22:16:04 +00:00
Felix Singer bf1de40853 {soc,superio}/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntax 
Replace `Subtract (a, b, c)` with `c = a - b`.

Change-Id: If6455ab2c91619f884abae227f1ac2e2c2af6ba9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-12 22:14:15 +00:00
Felix Singer fe33b4cb7c soc/intel/acpi: Replace Add(a,b) with ASL 2.0 syntax 
Replace `Add (a, b)` with `a + b`.

Change-Id: I0b7f22acf153fe02b471c196f8161fc0fa5a1450
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70624
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-12 22:13:00 +00:00
Felix Singer e4c30044f2 soc/intel/acpi: Replace Add(a,b,c) with ASL 2.0 syntax 
Replace `Add (a, b, c)` with `c = a + b`, respectively `a += b` where
possible.

Change-Id: I96390f565d6c1ca0f4e06db9ad07af784051650c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70622
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-12 22:12:13 +00:00
Felix Singer 9a37ae6ef6 mb/google/jecht/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntax 
Replace `LLessEqual (a, b)` with `a <= b`.

Change-Id: I4af47fdf5bab57c6bbfe417f55de35b074753120
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70621
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:11:13 +00:00
Felix Singer 5c8a94ae9e ec/lenovo/h8/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntax 
Replace `LLessEqual (a, b)` with `a <= b`.

Change-Id: I76855f9d4564fc08cd70456e2a0b1514cd73e35f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70620
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:09:35 +00:00
Felix Singer 8f75d79e74 soc/intel/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntax 
Replace `LNotEqual (a, b)` with `a != b`.

Change-Id: Ia1bd22a62ec2868324a88400e27ed52c9f169751
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70619
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:09:00 +00:00
Felix Singer 49384da933 mb/google/glados/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: Ic3a49828551b6da45999ff55539d5e3449d475e3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70598
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:07:41 +00:00
Felix Singer 01a06b203e mb/google/rambi/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: Ief985f8b7b14e8879a068140cb1f9b28c7336e94
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70597
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:07:16 +00:00
Felix Singer 096158d6e0 mb/google/cyan/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I9441988c0bf6d07641595a3b501c2af5230ba131
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70596
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:06:33 +00:00
Felix Singer 2ed8992d73 mb/google/slippy/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I50c1831c909163b8eb9b91d6ceb267bd8cc41e11
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70595
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:05:15 +00:00
Felix Singer b6cbda2717 mb/google/jecht/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I74a6c949fa08a6eb712c053137369242e20e78fe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70594
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:04:28 +00:00
Felix Singer edec4d9b9a soc/intel/braswell/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I7b74d026d0800df647fb0c981fa7865be492d3ac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70590
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:02:59 +00:00
Felix Singer 26c7672591 soc/intel/baytrail/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I9d50ddcb4427774681aedba945079f5d04401f07
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70589
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 22:01:02 +00:00
Felix Singer 31c099a7b8 soc/intel/icelake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I36137cbf63a36e68480029058f4426ed80ff6e3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70588
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 21:59:12 +00:00
Felix Singer c1913705ac mb/lenovo/s230u/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I710d9c8c767a688f423d5a7e3e2708eb6aef11fc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70587
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 21:58:32 +00:00
Felix Singer fef71fcebe mb/aopen/dxplplusu/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I4fa3942216f1638abeafa0c562f4d6a2a499254b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70586
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 21:58:08 +00:00
Felix Singer b8762ae2dc mb/intel/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I99f34d4c03b0687b8e0c2e4aee85f196679bcf52
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-12 21:45:10 +00:00
Felix Singer 43b5730962 soc/intel/acpi: Replace Decrement(a) with ASL 2.0 syntax 
Replace `Decrement (a)` with `a--`.

Change-Id: I5c9290aaa9fc969368d5934e4f48a75d915ca5ff
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-12 21:44:41 +00:00
Felix Singer 5cbf2be43a ec/clevo/it5570e/acpi: Replace Index(a, b) with ASL 2.0 syntax 
Replace `Index (FOO, 1337)` with `FOO[1337]`.

Change-Id: If035eac6b6eb06f79eb6596364bc41069ba42f70
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-12 21:43:31 +00:00
Felix Singer d056d87806 ec/purism/librem-ec/acpi: Use Printf() for debug prints 
Change-Id: Ie29511ad0b8e24feb478152009d7f4e8ed3ad26d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
 2022-12-12 21:42:56 +00:00
Felix Singer 89734cec05 mb/acer/aspire_vn7_572g/acpi: Use Printf() for debug prints 
Change-Id: Ie26b623a3848b929b83aad5931b1ecd90b342d2c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
 2022-12-12 21:42:27 +00:00
Elyes Haouas 8f53e20955 sb/intel/common/acpi_pirq_gen.h: Fix conflicting types for 'is_slot_pin_assigned' 
Found using 'Wenum-int-mismatch' (GCC-13: default with -Wall):
src/southbridge/intel/common/acpi_pirq_gen.c:69:6: error: conflicting types for 'is_slot_pin_assigned' due to enum/integer mismatch; have 'bool(const struct slot_pin_irq_map *, unsigned int,  unsigned int,  enum pci_pin)' {aka '_Bool(const struct slot_pin_irq_map *, unsigned int,  unsigned int,  enum pci_pin)'} [-Werror=enum-int-mismatch]
   69 | bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map,
      |      ^~~~~~~~~~~~~~~~~~~~
In file included from src/southbridge/intel/common/acpi_pirq_gen.c:8:
src/southbridge/intel/common/acpi_pirq_gen.h:91:6: note: previous declaration of 'is_slot_pin_assigned' with type 'bool(const struct slot_pin_irq_map *, unsigned int,  unsigned int,  unsigned int)' {aka '_Bool(const struct slot_pin_irq_map *, unsigned int,  unsigned int,  unsigned int)'}
   91 | bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map,
      |      ^~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors

Change-Id: Ie91947d00feaae42314ec2d1291f39d667a85346
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70387
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
 2022-12-12 18:20:55 +00:00
Sean Rhodes 9d1c9ee212 soc/apollolake: Add DPTF HIDs 
Add the HIDs that Windows uses for the DPTF driver.

Change-Id: Ic0cb4a45b5ebaf777a09bed1e5836e8afd873657
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66013
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 18:20:20 +00:00
Felix Held b3261661c7 cpu/x86/mtrr/mtrr: fix printk format strings 
Commit 4c3749884d ("cpu/x86/mtrr: Print cpu index number when set up
MTRRs for BSP/APs") added the CPU index number to some prints, but used
%x as format specifier. The cpu_index() call however has a return type
of unsigned long, so %lx needs to be used instead. For consistency, also
change the type of the cpu_idx local variable in commit_fixed_mtrrs to
unsigned long and adjust the printk format specifier accordingly.

TEST=The code builds again on my computer

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b68f8355932b2b75db5f453a0a735185b24b02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70664
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 15:21:46 +00:00
Felix Held d3690ee19c vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy config 
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2022-12-12 15:19:45 +00:00
Jeremy Compostella 355471aa74 drivers/pc80/vga: Fix coding style issues 
- Use `size_t' for iteration index variables
- Use the `VGA_COLUMN' macro definition instead of the hard-coded
  value

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Verified on Skolas

Change-Id: I1d6595871363ec7602219e72d1260df3722f64de
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70453
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-12-12 15:06:42 +00:00
Kane Chen 4c3749884d cpu/x86/mtrr: Print cpu index number when set up MTRRs for BSP/APs 
MTRR setup will be assigned to all APs. It's hard to debug
race condition without showing apic id.

Change-Id: Ifd2e1e411f86fa3ea42ed50546facec31b89c3e1
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
 2022-12-12 13:57:24 +00:00
Anil Kumar f945118f54 soc/intel/adl/acpi: add entries for HEC1 and SRAM to DSDT 
HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb:

device pci 16.0 alias heci1 on  end
device pci 14.2 alias shared_sram off end

This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel

TEST=Built and tested on brya to confirm errors are not seen.
BUG=b:260258765

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 13:55:46 +00:00
Bo-Chen Chen 7d94b2b489 mb/google/geralt: Add support for MIPI display 
Both eDP and MIPI interfaces are supported in geralt project, so we can
initialize the different displays according to the panel ID.

This patch also generalizes the display initialization. So
`configure_edp_panel_backlight` and `power_on_edp_panel` can be removed.

BUG=b:244208960
TEST=test firmware display pass for MIPI panel on MT8188 EVB.

Change-Id: I7ae9318f56c70446516e197635acaffb8197ab53
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70406
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 13:55:19 +00:00
Bo-Chen Chen c07ccd9aac mb/google/geralt: Put eDP panel data in panel_geralt.c 
Both eDP and MIPI interfaces are supported in geralt project. Therefore,
we put the eDP panel data in panel_geralt.c to have the consistent
interface `get_active_panel` function.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: Ib35b3cab31bae4109b9715242201425580339536
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70405
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 13:54:55 +00:00
Bo-Chen Chen 49465167a0 mb/google/geralt: Put MIPI panel data in panel_geralt.c 
There are eDP and MIPI panels supported in geralt. We put the panels'
specified functions - `power_on()` and `configure_panel_backlight()` in
panel_geralt.c. Also provide the common interface `get_active_panel()`
in panel.c to generalize the display initialization. Since each board
may support a different set of MIPI panels, we put the MIPI data in a
separate file panel_geralt.c.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: Ie928759e020a916f29f0364201a3cf202dc512c3
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-12-12 13:54:24 +00:00
Nick Vaccaro 80f38227cf mb/google/brya: fix GPP_H13 setting for brya0 and skolas 
The EN_PP3300_SD gpio (GPP_H13) was configured as a no-connect, but
should be configured as an output.

This change configures GPP_H13 on brya0 and skolas to be an output.

BUG=b:261901759
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot chromeos-bootimage" and verify skolas boots.

Change-Id: Ia3f01e877a5fea3af9a6e746523ed395f3af3b8a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70512
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 13:53:22 +00:00
Fred Reitberger 694ef4431b soc/amd/morgana: Remove emmc select 
Morgana does not have emmc, so do not select it.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib75618c137e825befc7384275f1a4ef9b5137b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70477
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 13:53:02 +00:00
Sridhar Siricilla d1237da6cc soc/intel/meteorlake: Enable SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID 
The patch enables CPPCv3 support for Intel Meteor Lake which is based
on hybrid core architecture.

TEST=Build code for Rex.

Change-Id: Iddf15f01a401eedf695f2dd07fbee0b643d143e2
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70511
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 13:52:02 +00:00
Arthur Heymans e0f08727e1 mb/ocp: Provide better defaults for UART 
The baudrate of the SOC console is always 57600 and on tiogapass the
0x2f8 COM port is also used by the SOL console.

Change-Id: Ia7bf9fbe10ec66f49c2c7b41938a1a33967c131a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70500
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 13:51:46 +00:00
Saurabh Mishra f339b63b02 vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.h 
Changes include:
- FirmwareVersionInfoHob.h is removed to use new header file
  FirmwareVersionInfo.h.

BUG=b:260183604
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-12 13:50:04 +00:00
Saurabh Mishra 16ba8e12fa soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2 
Changes include:
- Add config for Meteor Lake SoC to select FirmwareVersionInfo.h
  using 'DISPLAY_FSP_VERSION_INFO_2'

BUG=b:260183604
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-12 13:49:45 +00:00
Saurabh Mishra 997e9f74a1 vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.h 
Changes include:
- Add header file FirmwareVersionInfo.h

BUG=b:260183604
BRANCH=None
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: Ib5c843bb0dccd5db92f74148df3a17037988392c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69882
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-12 13:49:31 +00:00