Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The function exit()s on failure, and no callers check the return value.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As reported by Jody McIntyre. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
board_pciid_enables more readable.
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
> What real problem does this solve?
1. Next time someone adds a new struct member, we avoid mistakes of
ordering of initializers
2. we avoid mistakes in the first place.
The .x = y stuff was added for a (good) reason, I think this is an
improvement.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge.
The board uses GIGABYTE's patented BIOS failover technology, and at this point
we do not know how to control which of the two chips flashrom actually hits.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
incorrect license section.
- Remove the copyright listings and refer the reader to the source
files.
- Update the author list to those which have copyright messages in the
source files.
- Correct the license from GPL v2+ to (GPL v2, with some files under
later versions as well)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
flashchips.c over what's currently in flashrom HEAD.
The explicit initialization makes sure any future struct flashchip
reordering is not needed. (Except for the case where we need arrays
of some of the struct members.)
Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux@free.fr>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix that by throwing an error instead.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
There seem to be at least two versions of the board out there, and the
subsystem IDs changed between the versions.
Patch successfully tested on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* rename ich_check_opcodes to ich_init_opcodes.
* let ich_init_opcodes do not need to access flashchip structure:
. move the definition of struct preop_opcode_pair to a better place
. remove preop_opcode_pairs from 'struct flashchip'
. modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure
* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.
* fix a coding style mistake.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
support the MX29LV040C.
MX29LV040C probe and read support tested by khetzal on IRC.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch adds SB700 support to flashrom. The code for enabling the flash
rom is the same as for SB600. It was tested (read, write, verify) with an
ASUS M3A-H/HDMI which contains a Macronix MX25L8005.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Thanks to Niels Ole Salscheider for the problem report.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
flashrom used to exit 0 even if erase failed. Not anymore.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
SST_25VF512A_REMS
SST_25VF010_REMS
SST_25VF020_REMS
SST_25VF040_REMS
SST_25VF040B_REMS
SST_25VF080_REMS
SST_25VF080B_REMS
SST_25VF032B_REMS
SST_26VF016
SST_26VF032
W_25X16
W_25X32
W_25X64
Straight from the data sheets.
The REMS IDs help in case the RDID opcode is unavailable (due to opcode
lockdown) or unsupported by the chip.
Some day, we need to pair probe functions together with IDs. Multiple
pairs can exist per chip and duplicating chip definitions does not
really make sense.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Bug from r3791.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
If flashbase was set before probe_flash() it would only ever be used once, for
the very first flash chip probe.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jason Wang<Qingpei.wang@amd.com>
Reviewed-by: Joe, Bao <Zheng.Bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
unsupported functions, giving the user the impression that the
unsupported functions are tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This has been tested by Uwe Hermann on an RS690/SB600 board.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is the first chip which uses the infrastructure for alternative
erase commands, namely spi_chip_erase_60_c7().
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID
RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.
The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Peter Stuge