There is already a function with the name buffer_size(). Adding a local
variable with the same name will lead to the following error on older
GCC versions (e.g. version 4.4.7):
declaration of 'buffer_size' shadows a global declaration
To fix this rename the local variable to buffer_len.
Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Header contains ':' in copyright line. rmdoule is a typo
Remove the ';' and correct typo to rmodule.
BUG=N/A
TEST=N/A
Change-Id: I05b1fb80a81682646c9fba3d234de235b6bc9e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The GPT version must be "00 00 01 00" and the little endian should be
represented as 0x10000.
Please refer to: https://en.wikipedia.org/wiki/GUID_Partition_Table
Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/29767
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The purpose of this tool is to manipulate and get information about the
`Back Up Control, Top Swap` mechanism present on most Intel Southbridges.
This tool is initially written by Peter Stuge.
This tool makes it possible to have a backup mechanism for the
bootblock by using the southbridges Back Up Control Top Swap.
Sometimes it is also possible to circumvent vendor write protection mechanisms
in order to flash coreboot. An example of where this would be useful would be
the Lenovo Thinkpad X60 and T60.
Change-Id: I12cc2e91396f096fc979e23848e1929cb6c44fc5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18224
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Newer kernels only allow root to access the kernel log buffer.
In another case (cbmem) we use sudo to get past that, so we can
expect sudo to be available here, too.
Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/29670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Python 3 is the default Python interpreter on most modern systems.
Python 2 scripts must specify they should be run with Python 2 in their
shebang. Solves issue raised in CB:28953.
Change-Id: I9ace4afd668539c05e7ace30e255af50c7a069c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some Unix systems (GuixSD, NixOS) do not install programs like
Bash and Python to /usr/bin, and /usr/bin/env has to be used to
locate these instead.
Change-Id: I7546bcb881c532adc984577ecb0ee2ec4f2efe00
Signed-off-by: Yegor Timoshenko <yegortimoshenko@riseup.net>
Reviewed-on: https://review.coreboot.org/28953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Sometimes it is necessary to be able to see exact command lines used
when compiling and linking. Use the same scheme as some other
Makefile's - enable verbose output when variable V is set to 1.
TEST=tried building cbfstool with V=1, observed verbose output.
Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/29431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a test that, after cloning the repository to a temporary directory,
installs git hooks and attempts to do a good and a bad commit, expecting
the former to succeed and the latter to fail, thus testing the
`commit-msg` hook.
Change-Id: Icdaf0109c60cb5b6952b1a2468ab050a742e4201
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23281
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is so confusing, let's name it what it is ;)
Change-Id: I6f87e2f6912d886e241e03998fb4136fb28bc7b1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bind a volume for .ccache to the `docker-run-local` targets. By default
the current user's $(HOME)/.ccache will be used, it can be overridden
via the DOCKER_CCACHE variable.
Also rearrange some docker parameters to keep the target readable.
Change-Id: I7d0bdb3861ac56361cacfa74aaf8b45c4f135e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add an unprocessed flag (-U) which modifies how files are exported.
In the case of a compressed raw file, extract without decompressing.
In the case of a stage or payload, extract without decompressing or
converting to an ELF.
This can be useful for verifying the integrity of a stage or payload,
since converting to an ELF may not be a deterministic process on
different platforms or coreboot versions.
BUG=b:111577108
TEST=USE=cb_legacy_tianocore emerge-eve edk2 coreboot-utils chromeos-bootimage
cd /build/eve/firmware
/build/eve/usr/bin/cbfstool image.bin extract -r RW_LEGACY \
-n payload -f /tmp/payload_1 -U
START=$((16#`xxd -s 20 -l 4 -p tianocore.cbfs`))
SIZE=$((16#`xxd -s 8 -l 4 -p tianocore.cbfs`))
dd if=tianocore.cbfs skip=$START count=$SIZE bs=1 > /tmp/payload_2
diff /tmp/payload_1 /tmp/payload_2
rm /tmp/payload_1 /tmp/payload_2
Change-Id: I351d471d699daedd51adf4a860661877f25607e6
Signed-off-by: Joel Kitching <kitching@chromium.org>
Reviewed-on: https://review.coreboot.org/29616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add a `docker-run-local` target that is used as a template for the
local build targets (`docker-build-coreboot`, `docker-abuild`, and
`docker-what-jenkins-does`).
Note this changes the user for `docker-what-jenkins-does` which has
(ccache) issues if it's not `root`. Will be fixed in a follow-up.
Change-Id: I9088fb9211726cddc37b17ddf70170c2c382679e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build CBFS with original code, run objdump and saved output. Added
modifications, build cbfs again, run objdump again, compared objdump outputs.
Change-Id: I30187de8ea24adba41083f3bfbd24c0e363ee4b8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add a `util/gitconfig/test` subdirectory which will contain tests to run
as executable files, add a helper script.
Add a timeout test that verifies that gitconfig completes in under two
seconds (typical run time is ~30 ms). Add gitconfig tests to the
`testing` Makefile under the `test-tools` target.
Change-Id: Id46f905b9f782e67be97a65d10045c3345dc996b
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23280
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The gerrit reviewers plugin has a certain configuration format. Teach
maintainers to emit it when called with -print-gerrit-rules.
Change-Id: I92cfc905e0c1b03b7cf793a4324c392140a22060
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
First new option is -debug.
Change-Id: Ia6e9b3675449a0b1e6f5d7526ee999f925eaadb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Help automated tools make sense of the output.
Instead of "[name 1 <email> name 2 <email>]", it now prints
"name 1 <email>, name 2 <email>". As long as there are no commas in the
maintainer names, they can be split easily.
Change-Id: I4a254f566404b081a08923bc7ceb49f02039aa2a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29604
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of checking only for three cases, just use a glob parser (that
translates the glob to regex).
After that, maintainers src/arch/x86/memlayout.h emits:
src/arch/x86/memlayout.h is in subsystem X86 ARCHITECTURE
Maintainers: []
src/arch/x86/memlayout.h is in subsystem MEMLAYOUT
Maintainers: [Julius Werner <jwerner@chromium.org>]
The latter entry was invisible to the maintainers tool because its path
description wasn't in one of the supported formats.
Change-Id: I7e5cf4269415269552e35f2c73952ce3dff487e1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Without this change, the tool only reports the first hit. We want to see
all of them.
Change-Id: Ib59b13c50b61c48e3cb200bf57e28c9453590819
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
ME Cleaner's component has an entry specifying its website, which this
parser didn't know how to handle. Avoid the resulting warning.
While at it, de-C the switch statement and make it work go-style. This
also fixes "R" statements being ignored.
Change-Id: Ifc23e28daba9d85bf690557a80134accea8bed21
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Clear remalloced memory
* Fix check for invalid VBT offset in header
* Fix VBIOS checksum generation
* Fix VBIOS size field
* Align VBIOS size to multiple of 512
* Reassign pointers after use of remalloc
* Don't leak on error path
Current version is enough to allow the proprietary Windows Intel GMA
driver to find the VBT in the legacy VBIOS area and it doesn't BSOD
any more.
The LVDS screen remains black, due to an unknown issue with the
proprietary driver, while the VGA works.
Tested with libgfxinit and native graphics init.
Change-Id: If07b1bb51d8fb3499d13102f70fedb36c020fb72
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The foreword mentioned that you need a gerrit account, but not how to
have git push with the right credentials.
To ease onboarding, point out where to get them.
Change-Id: I0b022bc064e3bc89568617c1a3a3e0e5236ba520
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If we build one of the `all*` targets, build Clang first. Compiling
Clang (just for the host arch, I assume) takes more than half of the
time of the default build. When run as a separate step, we can make
use of Docker's cache if any step after Clang fails.
Change-Id: If67b458cde656f1dc6774215f6a575a48d12b797
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The choice of `gnat-6` was originally an optimization because the meta-
package `gnat` installs not only the current GNAT version but also other
unwanted (and hard to explain) dependencies. Later it was necessary
because GCC 8 couldn't compile our older crossgcc.
Now that we switched crossgcc to GCC 8.1, `gnat` should be fine.
Change-Id: Ica8a1f9d6d71a74ffc4ec76aa0cfbe4b604cde1b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29454
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current version in debian:sid is incompatible with our crossgcc
version. But it turned out that we don't use the optimization features
enabled by libisl at all: crossgcc builds with and without (a proper
version of) libisl-dev installed generate the same coreboot binaries.
Change-Id: I9f9115d8ab33cbe11aa77f16c98465e1c1dedeac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
As by afda56e1ad (buildgcc: Drop libelf/elfutils), it's not used (atm).
Change-Id: I3124cb6db5975c21e635636babe700adb0f8cd8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Global variables are considered a bad practice.
Change-Id: I652a8da75498f871a53eb7509f6145c4842e3373
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/27810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The GPIO register dumper code for the LynxPoint family PCH chips
(Intel 8 Series and C220 Series) was incorrectly using a
shortened version of the LynxPoint-LP GPIO register map.
Switched to the correct register map for the affected chipsets.
Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f
Signed-off-by: Fehér Roland Ádám <feherneoh@gmail.com>
Reviewed-on: https://review.coreboot.org/29167
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix a typo and make comments more consistent (start with
capital letter).
BUG=None
TEST=None
Change-Id: I97bff5e05596fc6973f0729e276a2e45b291120d
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/29025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This is a no-op on non-FSP systems, but enables using it when supported.
Change-Id: I66fe9b8587753ea017e13a752a7728e47287e9a0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
There is no datasheet available for this SuperIO, but dumping all
possible registers on a Dell Optiplex GX520 resulted in data that was
similar to other supported chips. Data also matches what is set in the
BIOS, e.g. the parallel and serial ports' addresses.
Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The SCH3112, SCH3116 and SCH5127 were lacking a pin dump. Since their
datasheets are available, add their pin dumps.
The SCH3112, SCH3114 and SCH3116 are almost identical, they only differ
in the number of serial ports. Some values in the SCH3114 dump were
inaccurate, that has been fixed as well.
Datasheets used:
- SCH311X: DS00001872A
- SCH5127: DS00002081A
Change-Id: Ic985526be9b09e0452eaf883904dfaf709b7e907
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add Makefile dependency to source file
* Add argument support
* Add help support
* Print usage on wrong arguments
* Add support for parsing VBT binary file
* Add support for parsing PCI Option ROM
* Add support for writing VBT binary file
* Add support for patching PCI Option ROM
* Keep support for accessing legacy VGA area Option ROM
* Keep support for dumping VBT contents to stdout
Allows to extract VBT, analyse VBT and patch PCI Option ROMs as needed.
The required arguments have been changed:
./intelvbttool --<SOURCECMD> [filename] --<DESTCMD> [filename]
SOURCECMD set the VBT source. Supported:
inlegacy : Legacy BIOS area at phys. memory 0xc0000
invbt : Read raw Intel VBT file
inoprom : Read VBT from Intel Option ROM file
DESTCMD set the VBT destination. Supported:
outdump : Print VBT in human readable form
outvbt : Write raw Intel VBT file
patchoprom: Patch existing Intel Option ROM
Any combination of SOURCECMD and DESTCMD is possible.
Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Until now, autoport used to create a dummy "romstage.c", then write
romstage code to "early_southbridge.c". While it works, it makes more
sense to write to "romstage.c" instead, as virtually all mainboards do.
Change-Id: If9f9375f9a659e7e685de5f884163813261fa656
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28851
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, an entry being removed is cleared only if the next entry
is also null or deleted.
This patch ensures the entry being removed is cleared regardless of
the next entry type.
BUG=chromium:889716
BRANCH=none
TEST=Run cbfstool bios.bin remove -n ecrw.
Verify bios.bin has 0xFF in the space of the removed entry.
TEST=Run cbfstool bios.bin remove -n fallback/payload (located at the end).
Verify fallback/payload is removed.
TEST=Run sign_official_build.sh on recovery_image.bin. Extract
firmware contents from chromeos-firmwareupdate in the resigned image.
Run 'futility vbutil_firmware --verify' for vblock_A's and FW_MAIN_A
extracted from bios.bin. See the bug for details.
Change-Id: I62540483da6cc35d0a604ec49b2f2b7b11ba9ce5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/28886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
One occurence of this parameter was changed from LBROOT to CBROOT in
f8ee1806ac ("Rename almost all occurences of LinuxBIOS to coreboot.").
Change the others, too.
Change-Id: Ic0da24c32cd6d2f0577de037b5463c800f455786
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This board doesn't support the newest RISC-V Privileged Architecture
spec (1.10), and it's based on an FPGA so it's a moving target.
Now that there's actual RISC-V silicon out there (from SiFive),
mb/lowrisc/nexys4ddr will only continue to bitrot.
Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
They allow reducing the visible set of options to remove clutter.
Change-Id: I18c953c7feae23c0752392a2bf8f49783c17310e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Since CBMEM console became a ring buffer, logs from several boots can be
stored. We are only interested in the current boot.
> -c | --console: print cbmem console
> -1 | --oneboot: print cbmem console for last boot only
For CBMEM time stamps only the time stamps of the current boot are
stored, so only the commands for the CBMEM console need to be adapted.
Change-Id: I18caa4aeebbd5576b9e218d176a7db5a8e868b74
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
For devices supporting both Linux and Windows, we may find some ACPI
devices that only need drivers in Linux and should not even be shown in
Windows Device Manager UI.
The new 'hidden' keyword in device tree 'device' statement allows
devices sharing same driver to call acpi_gen_writeSTA with different
values.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: Iae881a294b122d3a581b456285d2992ab637fb8e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.
Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.
Further changes are needed in the bootblock
Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Change-Id: Icbf21b02d3092815bbe876eceea72ebba8dd54da
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This SuperIO is supported by coreboot and used in two Asus boards. However,
superiotool was lacking a register dump for this chip. Add the corresponding
data from datasheet W83667HG-B revision 1.3 into superiotool.
The SuperIO's datasheet was obtained by requesting it to Nuvoton.
Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Otherwise it reduces its expectations on what as and ld take in terms
of arguments, which breaks some edk2 related builds because tons of
-I$path_to_stuff arguments aren't passed along.
Change-Id: I53f87442de03d5ead8a6632d3102d5502065b828
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Werner Zeh