Commit Graph

235 Commits

Author SHA1 Message Date
Karthikeyan Ramasubramanian 0ab04d2851 util/amdfwtool: Add IKEK key for Trusted Application
This binary file is required for use by Trusted Applications that
execute in PSP.

BUG=b:229947314
TEST=Build and boot to OS in Skyrim.

Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-05 14:48:31 +00:00
Zheng Bao 993b43f2be amdfwtool: Use command line option use-combo to decide if use combo
The macro PSP_COMBO is removed and instead use the flag use_combo. As
long as this flag is false, the amdfwtool behaves the same way as the
macro does.

Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25 14:48:16 +00:00
Zheng Bao 96a3371a72 amdfwtool: Change the name of macros for 'BHD'
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it
clear it is for level 2. The 'BHD2' is misleading, which is going to
be used for combo entry. The definition in psp_verstage is also changed.

Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-25 14:46:12 +00:00
Karthikeyan Ramasubramanian ad06bae7b1 util/amdfwtool: Maintain one copy of PSP Level2 entries
AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot
A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which
use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2
entries in each FW slot is redundant and space-consuming. Introduce
option to maintain only one copy of PSP Level2 entries and point to it
from both slots A & B.

BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added
to each FW slot. This achieved a space saving of 1.5 MB in each FW slot.
Before:
apu/amdfw                      0x415fc0   raw           3043328 none
After:
apu/amdfw                      0x415fc0   raw           1556480 none

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-14 15:39:15 +00:00
Zheng Bao c3007f3877 amdfwtool: Add a flag to record the second gen instead of romsig
This is for future feature combo, which gets the soc id from fw.cfg in
a loop instead of the command line, and the romsig is not set until
fw.cfg is processed.

Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-13 23:25:00 +00:00
Zheng Bao 487d04540b amdfwtool: Add a macro to set explicitly second gen for old SOCs
It is more reasonable than getting the value from memset.

For the reserved bits, keep them as they were for old SOCs.

Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-05 17:45:58 +00:00
Felix Held 11b0d360ba util/amdfwtool/data_parse: fix SPL table handling regression
Use the SPL table binary from the config file if no override is
specified via the spl-table command line argument. This fixes a
regression caused by commit 6c5ec8e31c
(amdfwtool: Add options to support mainboard specific SPL table).

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-03 17:06:48 +00:00
Felix Held f8e2e47e2b util/amdfwtool: use ISH support for Sabrina SoC
The PSP in the Sabrina SoC uses the image slot header to find the second
level PSP directory table, so it needs the ISH to be generated.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9e6308854147c9f6f72d722215c833ee86ee4f94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63186
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:42:14 +00:00
Felix Held b18a4c7d0d util/amdfwtool: add Sabrina SoC type
Add PLATFORM_SABRINA to the enum of supported platforms and integrate it
into the existing code.

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe52b44395619f697686bd900a522562abbe7646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 23:41:53 +00:00
Felix Held 830add6e27 util/amdfwtool: select A/B recovery when ISH is used
In newer AMD SoCs, the image slot header is used in the AMD A/B recovery
scheme, so set recovery_ab to true when need_ish is true. Also move the
block of code before the process_config call, since that call will
already use the recovery_ab field of the cb_config struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:41:48 +00:00
Felix Held 21a8e381ea util/amdfwtool: use table-relative addressing in ISH case
When the image slot header (ISH) is used, the addresses in the PSP and
BIOS directory tables need to be relative to the beginning of the table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 22:20:04 +00:00
Zheng Bao 3a6ab474e0 amdfwtool: Clear the whole byte of EFS_GEN
Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-29 15:41:20 +00:00
Zheng Bao fdd47ef1e6 amdfwtool: Add ISH header support for A/B recovery layout
Image Slot Header (ISH) is a new feature.
The rom layout for A/B recovery with ISH:
EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A
              0x4A -> ISH B -> PSP L2 B -> BIOS L2 B

The newer 55758 will updated about the boot priority and update retry
in ISH header.

Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27 15:24:15 +00:00
Felix Held 5f18bb75fb util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types
Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware
table entries, so add those as a preparation for Sabrina support.

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-27 15:21:21 +00:00
Zheng Bao fb9b784ca2 amdfwtool: Change the some FW's level for A/B recovery
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.

The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.

Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-23 20:17:45 +00:00
Zheng Bao 52a1898d44 amdfwtool: Check the length of matching string before accessing
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.

Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-21 16:55:46 +00:00
Zheng Bao 4df5af87be amdfwtool: Clear struct match before regular expression matching
If it is not cleared and the number of strings is fewer than last
iteration, the match[3] will keep the last value, which actually
should be empty.

Add assert to make sure the level is a legal value.

BUG=b:222038278

Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-09 14:02:21 +00:00
Zheng Bao fdb0294846 amdfwtool: Check the real length of PMU string
The length should be checked before the PMU_STR_INS_INDEX(th) character
is accessed, otherwise it is going to an access violation.

Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-24 00:41:45 +00:00
Zheng Bao e220faa18a amdfwtool: Add entries for PMUI & PMUD with instance 2
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21 23:48:57 +00:00
Zheng Bao 990d154898 amdfwtool: Add support for AMD's BIOS A/B recovery feature
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
              0x4A -> PSP L2 B -> BIOS L2 B

The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.

To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.

TEST=Majolica(Cezanne)

Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 23:47:20 +00:00
Zheng Bao 1a9e54302b soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.

Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 21:29:50 +00:00
Zheng Bao 6c5ec8e31c amdfwtool: Add options to support mainboard specific SPL table
For the generic board which uses Cezanne, we use the generic SPL
table. For the Guybrush Chromebook, we need to use a customized SPL
file.

BUG=b:216096562

Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12 16:36:07 +00:00
Zheng Bao ab84fd7605 amdfwtool: Add SPL support
SPL: Security Patch Level
The data in SPL is used for FW anti-rollback, preventing rollback of
platform level firmware to older version that are deemed vulnerable
from a security point of view.

BUG=b:216096562

Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07 18:38:40 +00:00
Zheng Bao 6fff2497b1 amdfwtool: Upgrade "relative address" to four address modes
Address Mode 0: Physical Address, bit 63~56: 0x00
Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40
Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80
Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0

It is the expanding mode for simple relative address mode, for which
address_mode equals 1.

Only mode 2 is added. We need to record current table base address and
calculate the offset. The ctx.current_table is zero outside the
table. When it goes into the function to integrate the table, it
should backup the old value and get current table base. Before it goes
out the function, it should restore the value.

If the table address mode is 2, the address in each entry should be
also add address mode information. If not, the address mode in entry
is meanless.

The old mode 0,1 should be back compatible.

Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-16 14:35:52 +00:00
Zheng Bao da83d2c97f amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses "binary relative"
offsets and not "x86 physical MMIO address" like gen1.

The field additional_info in table header can tell if the absolute or
relative address is used.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

The related change in psp_verstage has been uploaded.
https://review.coreboot.org/c/coreboot/+/58316

The relative mode is the mode 1 of four address modes. The absolute
mode is the mode 0. Later we will implement mode 2. Not sure if mode 3
is needed.

It needs to be simple to work with psp_verstage change to make SOC
Cezanne work quickly. This patch is defacto a subset of
    https://review.coreboot.org/c/coreboot/+/59308
which implements the framework of address mode and covers mode
0,1,2. Some hardcode value like 29 can be removed in 59308.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-14 16:15:52 +00:00
Zheng Bao 570645dc2a amdfwtool: Call the set_efs_table for Stoneyridge
Related to https://review.coreboot.org/c/coreboot/+/58555
commit-id: 35b7e0a2d82ac
In 58555, we added the SOC ID for Stoneyridge in amdfwtool
command line. But it raised building error because it then called
"set_efs_table" without setting SPI mode. So we skipped calling that.

But in set_efs_table, it has case for Stoneyridge. The boards also
need to have this setting. So we remove the skipping and give the
proper SPI mode in mainboard Kconfig.

Change-Id: I24499ff6daf7878b12b6044496f53379116c598f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:29:48 +00:00
Zheng Bao 6e2c5a3d18 amdfwtool: Set flag comboable as bool type
Fix the CL:
https://review.coreboot.org/c/coreboot/+/58942
The type comboable was int but set as true.

Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:28:59 +00:00
Zheng Bao b749d3f0d2 amdfwtool: Add a union for combo and psp directory
For combo layout, this is for combo header.
For non-combo layout, this is for PSP directory.

Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:28:47 +00:00
Zheng Bao 6bc300d8d5 amdfwtool: Set soc name for Stoneyridge
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table
is not called. Keep it unchanged.

Change-Id: I0e82188ce64733420a578446e22a077ef789be92
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 10:06:39 +00:00
Zheng Bao 5164e4b03f amdfwtool: Pack out-of-bounds check into a function and move
Need to check the FWs number limit several times. So pack the
duplicated steps into a function. And do it before access the new
entry.

Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-11 14:40:45 +00:00
Zheng Bao ba3af5e2ff amdfwtool: Change the flag value to type bool
Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:56:19 +00:00
Zheng Bao edd1e360f4 amdfwtool: Fix the parameter point to NULL instead of integer
Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:55:35 +00:00
Zheng Bao 33351336f8 amdfwtool: Change the definition of level to a bitwise form
Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:55:29 +00:00
Zheng Bao eb0404e8bf amdfwtool: Add PSP ID for combo and ISH header for A/B recovery
Nobody calls the function until combo or A/B is added, so suppress the
warning for now.

Test=Majolica (Cezanne)

Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-29 14:26:22 +00:00
Felix Held ad68b07d45 util/amdfwtool: rename PSP related embedded_firmware struct elements
The element at offset 0x14 in the embedded_firmware struct is the
pointer to the combo PSP directory header, so rename it from comboable
to combo_psp_directory to clarify that this is not a flag, but a pointer
to a data structure. Also rename psp_entry to psp_directory since it
points to the PSP directory table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19 12:35:08 +00:00
Zheng Bao b1fb8cebf8 amdfwtool: Add an optional column of level
The value of level defined in table is the default one. We now give an
extra option in config file to change this value so some FWs can be
dropped in a more optimized way.
For the non A/B recovery mode, The value could be L1, L2, Lb or Lx,
which are level 1, leve 2, level both and using default value. If it
is empty or Lx, left the level in table unchanged.

Give a redundant field [12bxBX] in regular exprssion for A/B recovery
which will be done later.

Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23 06:26:47 +00:00
Zheng Bao 2079589999 amdfwtool: Detect the flag multilevel to decide the actual value
To save the space for FW, some of the FWs are going to be defined as
LVL2 entries. To be compatible to "flattened" layout, we still drop
the LVL2 entry to level1 if there is only one level.

Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-17 14:48:30 +00:00
Zheng Bao 535ec536ea amdfwtool: Add new SOC mendocino
Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-15 16:50:44 +00:00
Zheng Bao 481661e313 amdfwtool: Add flag for multi FW level to the struct amd_cb_config
This change can make the code be more flexible. And later we will use
amd_cb_config to transfer parameters.

Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:06:03 +00:00
Zheng Bao dac446165e amdfwtool: Copy string in a safer way
The issue is reported by Coverity. Using strcpy or strcat copying
string without checking length may cause overflow.

BUG=b:188769921

Reported-by: Coverity (CID:1438964)
Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:05:48 +00:00
Kangheui Won 275ade9539 Revert "amdfwtool: Use relative address for EFS gen2"
This reverts commit 0fc87e31e0.

Reason for revert: Breaks psp_verstage in guybrush

BUG=b:182477057

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:45:10 +00:00
Zheng Bao ec5a5d7abf amdfwtool: Fix the NULL pointer in parameters
Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08 18:52:00 +00:00
Zheng Bao 0fc87e31e0 amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses
"binary relative" offsets and not "x86 physical
MMIO address" like gen1.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-08 16:04:09 +00:00
Zheng Bao b035f58940 amdfwtool: Null check the pointers before using them
BUG=b:188769922

Reported-by: Coverity (CID:1438963)
Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:52:40 +00:00
Zheng Bao addf340adf amdfwtool: Add missing license header
Change-Id: Id466e733d421602cfe0403ead95e417f0bb37eb4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09 05:17:25 +00:00
Zheng Bao 6be1ab67e2 amdfwtool: Move EFS related definitions to header file
EFS: Embedded Firmware Structure

These structs and macros are defined in PSP specs(#55758).
They are supposed to be used by all C sources.

Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09 05:17:18 +00:00
Zheng Bao 826f1c4610 amdfwtool: Print the entry type when dumping the firmwares
Change-Id: I07bf10e16a42a2b2ab784ee6ac4a4465b7412da6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07 17:11:43 +00:00
Zheng Bao e8e6043489 amdfwtool: Set the region_type as 0 for entry "BIOS level 2"
This region_type is actually not used. But we need to set it
explicitly as a known value.

We can refer "PSP spec #55758" or the link below:
   https://doc.coreboot.org/soc/amd/psp_integration.html

Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07 17:11:24 +00:00
Nikolai Vyssotski 1965f650ea amdfwtool:cezanne: use correct bootloader binary for whitelist support
PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type
0x73 entry and not type 0x01 (stage1 bootloader). We will also need to
change WHL BL filename (Type0x01->Type0x73) in a separate CL.

BUG=b:181135622

Change-Id: I71539a2065546547edc8a2621474cd1388b6434b
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-18 10:00:13 +00:00
Zheng Bao 806892a347 amdfwtool: Remove the misleading option characters
Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-05-18 05:56:55 +00:00
Zheng Bao 6f0b361aee amdfwtool: Cleanup the message of help
1. Wrap the long lines.
2. Align the message.
3. Add new SOC name, Cezanne.
4. Fix the cases.

Change-Id: Id537d7c9b77641289274c1b2b6f606e2be37ac6b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-30 23:15:26 +00:00
Martin Roth d509076044 util/amdfwtool: Clean up Makefile
- Add method to disable warnings as errors
- Add help target
- Add phony targets to .PHONY

BUG=None
TEST=make all; make help; make all WERROR=""

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icd0cfd3e2579c9016ebb616e371d1076a5a171b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16 08:10:23 +00:00
Martin Roth 90baf6a403 util/amdfwtool: Enable warnings as errors
BUG=None
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7746430c24dd052c435561236454b456bc597517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16 08:10:12 +00:00
Martin Roth a8e31caee8 util/amdfwtool: Fix all warnings
Fixes these warnings:

warning: alignment 1 of 'struct _psp_directory_table' is less
than 16 [-Wpacked-not-aligned]

warning: alignment 1 of 'struct _psp_combo_directory' is less
 than 16 [-Wpacked-not-aligned]

In function 'find_register_fw_filename_bios_dir':
warning: implicit conversion from 'enum _amd_fw_type' to
'amd_bios_type' {aka 'enum _amd_bios_type'} [-Wenum-conversion]

BUG=None
TEST=Build and verify binaries are identical.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I761d9893ac6737b42af96c4b2a57c5a4fc61ab05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16 08:09:35 +00:00
Zheng Bao b993cb2d6c amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)
Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-03 13:48:51 +00:00
Patrick Georgi d92d7cb515 util/amdfwtool: Add "all" target to Makefile
The test-tools make target requires it.

Change-Id: I20819f8d587e6b3a472cdc32751e9edf505d5ba6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28 09:27:46 +00:00
Felix Held e862a004d7 util/amdfwtool,post: add missing distclean target
Without this target some spurious errors occurred when running make
distclean at the top level of coreboot.

Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49227
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 21:10:51 +00:00
Idwer Vollering 93df1d9cfa util/amdfwtool: portability fixes for FreeBSD
Add the stdint.h header, and drop the GLIBC section from amdfwtool.h to build this tool on FreeBSD as well as Linux.

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I295fd308b0f5e2902931f02c9455823a614976de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-31 16:06:58 +00:00
Zheng Bao bf29a0d21f amdfwtool: Add support of cezanne and renoir
Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:34:15 +00:00
Zheng Bao 5caca947b2 amdfwtool: Register APCB and APCB_BK respectively
We took the assumption the APCB(0x60) and APCB_BK(0x68) are the
same file. For picasso, they are. For later programe, they are not.

Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11 20:04:02 +00:00
Marshall Dawson 13ec029145 util/amdfwtool: Fix EFS generation polarity
The DWORD used to indicate the Embedded Firmware Structure's generation
uses 1 to indicate a first-gen structure, e.g. a SPI device's erased
value of 0xffffffff.  A 0 in bit 0 is how Client PSPs will interpret
the structure as designed for second-gen.

This change and the original addition should have no effects on
any current products as none interpret offset 0x24.

BUG=b:158755102
TEST=inspect EFS in coreboot.rom

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11 19:36:23 +00:00
Felix Held ea3417b5eb util/amdfwtool: add missing zero-initialization for local variable
Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47817
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21 19:40:33 +00:00
Zheng Bao 5014373edd amdfwtool: Move the MP2CFG checking to category of BIOS data
Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-17 08:07:12 +00:00
Zheng Bao 3384e4a709 soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 09:42:18 +00:00
Zheng Bao 77a2c67dfe amdfwtool: Change all error output to fprintf stderr
Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 09:42:04 +00:00
Zheng Bao 9e90807b40 amdfwtool: Add an option to show debug message
Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-04 09:41:58 +00:00
Patrick Georgi 8aa087ece6 .gitignore: Ignore .test/.dependencies globally
These were originally ignored only inside util/ but these files
shouldn't be tracked anywhere.

Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-31 18:21:36 +00:00
Zheng Bao c5e28abaf8 amdfwtool: Take a config file instead of command line parameters
To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.

BUG=b:154032833
TEST=Build & boot on mandolin

Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30 12:10:04 +00:00
Patrick Georgi 6065f616eb .gitignore: Split into subdirectory files
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.

Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 07:05:27 +00:00
Zheng Bao 9c8ce3e423 amdfwtool: Remove the assumption of ROM_SIZE
Every platform passes (and need to) the --flashsize to the command
parameter, so we remove the macro definition about a built-time
romsize defined in Makefile.

Change-Id: I894e833ed23a7da38b36986b624e7dcdf1f4090c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:46 +00:00
Zheng Bao 473969163d amdfwtool: Use a variable to get the return value of write
New Jenkins complaint about the original code that return
value gets to nowhere. Fix that with a new variable.

Change-Id: I8099b856ccb751dc380d0e95f5fe319cc3e2c6cc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45812
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 08:37:37 +00:00
Zheng Bao 7698a55202 amdfwtool: Clean up the Makefile of amdfwtool
Add Makefile.inc to compliant with other tools.
Makefile is kept for building amdfwtool by typing make
in the folder.

Change-Id: I3688d93de4459f5f838955892086b4b9bf30a9b8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:28 +00:00
Zheng Bao 6d402acbc0 amdfwtool: Fix the gcc warning about sign comparison
New (maybe) compile tool complains the warning below.
warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
Fix all of them.

Change-Id: I59624326233284e6c3595df49625563254949c45
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-02 16:01:45 +00:00
Martin Roth b1f648fc5c util/amdfwtool: Add PSP verstage signature entry
Add the field for the PSP verstage signature entry.  This adds the
public key signing token to the PSP Directory table to verify the signed
PSP verstage binary

BUG=b:166100797
TEST=Build in a file and verify that it's present with the correct ID.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7525045d8746b6857979d07b02758ab4d4835026
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03 16:30:14 +00:00
Martin Roth eca423b44f util/amdfwtool: Fix warning taking address of packed struct member
GCC9 introduced a new warning [-Waddress-of-packed-member].  This
is giving the following warning when building amdfwtool: warning: taking
address of packed member of ‘struct _bios_directory_entry’ may result in
an unaligned pointer value. Looking at the definition of the struct, it
looks like this is probably true.

Since the function being called doesn't read from the values, zeroing
them out in the beginning of the function, the code just passes pointers
to the temporary variables without initializing them.

BUG=None
TEST=Build & use AMD firmware table.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03 16:25:40 +00:00
Martin Roth 48dd9fe21f util/amdfwtool: Refactor APOB_NV requirements
amdfwtool currently assumes that we MUST have an apob_nv area if we
have an aopb.  This is not required, so if neither the apob_nv size or
base are specified, just move on.

BUG=b:158363448
TEST=Build an image with no APOB_NV region.  Dump regions to show that
it's not there.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21 18:46:58 +00:00
Matt Papageorge be4376c6c6 util/amdfwtool: Add support for EFS SPI values for F17h and F15h
The Embedded Firmware Structure contains various SPI parameters for
the PSP to program. This change adds support to amdfwtool for
populating these values as well specifying SOC Family and Model.

BUG=b:158755102
TEST=Read EFS values at appropriate offsets using a hex editor. Boot
test on Tremblye and Morphius.

Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:06:10 +00:00
Martin Roth 9455474f1b util/amdfwtool: Add option for setting PSP/FW shared memory location
This tells the PSP where in main memory to copy the vboot workbuf.

BUG=b:152576063
TEST=Build sharedmem destination into AMDFW, verify shared memory
gets placed at that location.

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08 14:19:24 +00:00
Martin Roth 37305e78fc util/amdfwtool: update to allow building in any location
For the verstage-on-PSP implementation, we need 2 additional copies
of the AMD firmware tables at non-standard locations.  These are
for RW-A & RW-B fmap regions.  This change allows us to build the
AMD firmware tables into those regions.

BUG=b:148767300
TEST=boot with psp_verstage, verify boot location

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I7f841db8617b953dc671a9c12576145f85263581
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08 14:08:20 +00:00
Rob Barnes 30ce0f383f util/amdfwtool: Fix MAX_PSP_ENTRIES value
Had to increase MAX_PSP_ENTRIES to accommodate the 16 APCBs we have
the ability to add.

BUG=b:150862063
TEST=Boot Trembyle
BRANCH=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I64eccfa28839768788f53327caf187a564842162
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2090323
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21 22:30:27 +00:00
Patrick Georgi 7051707129 treewide: Replace BSD-3-Clause and ISC headers with SPDX headers
Commands used:
perl -i -p0e 's|\/\*[*\s]*Permission[*\s]*to[*\s]*use,[*\s]*copy,[*\s]*modify,[*\s]*and.or[*\s]*distribute[*\s]*this[*\s]*software[*\s]*for[*\s]*any[*\s]*purpose[*\s]*with[*\s]*or[*\s]*without[*\s]*fee[*\s]*is[*\s]*hereby[*\s]*granted,[*\s]*provided[*\s]*that[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice[*\s]*and[*\s]*this[*\s]*permission[*\s]*notice[*\s]*appear[*\s]*in[*\s]*all[*\s]*copies.[*\s]*THE[*\s]*SOFTWARE[*\s]*IS[*\s]*PROVIDED[*\s]*.*AS[*\s]*IS.*[*\s]*AND[*\s]*THE[*\s]*AUTHOR[*\s]*DISCLAIMS[*\s]*ALL[*\s]*WARRANTIES[*\s]*WITH[*\s]*REGARD[*\s]*TO[*\s]*THIS[*\s]*SOFTWARE[*\s]*INCLUDING[*\s]*ALL[*\s]*IMPLIED[*\s]*WARRANTIES[*\s]*OF[*\s]*MERCHANTABILITY[*\s]*AND[*\s]*FITNESS.[*\s]*IN[*\s]*NO[*\s]*EVENT[*\s]*SHALL[*\s]*THE[*\s]*AUTHOR[*\s]*BE[*\s]*LIABLE[*\s]*FOR[*\s]*ANY[*\s]*SPECIAL,[*\s]*DIRECT,[*\s]*INDIRECT,[*\s]*OR[*\s]*CONSEQUENTIAL[*\s]*DAMAGES[*\s]*OR[*\s]*ANY[*\s]*DAMAGES[*\s]*WHATSOEVER[*\s]*RESULTING[*\s]*FROM[*\s]*LOSS[*\s]*OF[*\s]*USE,[*\s]*DATA[*\s]*OR[*\s]*PROFITS,[*\s]*WHETHER[*\s]*IN[*\s]*AN[*\s]*ACTION[*\s]*OF[*\s]*CONTRACT,[*\s]*NEGLIGENCE[*\s]*OR[*\s]*OTHER[*\s]*TORTIOUS[*\s]*ACTION,[*\s]*ARISING[*\s]*OUT[*\s]*OF[*\s]*OR[*\s]*IN[*\s]*CONNECTION[*\s]*WITH[*\s]*THE[*\s]*USE[*\s]*OR[*\s]*PERFORMANCE[*\s]*OF[*\s]*THIS[*\s]*SOFTWARE.[*\s]*\*\/|/* SPDX-License-Identifier: ISC */|s' $(cat filelist)

perl -i -p0e 's|(\#\#*)\s*Permission[\#\s]*to[\#\s]*use,[\#\s]*copy,[\#\s]*modify,[\#\s]*and.or[\#\s]*distribute[\#\s]*this[\#\s]*software[\#\s]*for[\#\s]*any[\#\s]*purpose[\#\s]*with[\#\s]*or[\#\s]*without[\#\s]*fee[\#\s]*is[\#\s]*hereby[\#\s]*granted,[\#\s]*provided[\#\s]*that[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice[\#\s]*and[\#\s]*this[\#\s]*permission[\#\s]*notice[\#\s]*appear[\#\s]*in[\#\s]*all[\#\s]*copies.[\#\s]*THE[\#\s]*SOFTWARE[\#\s]*IS[\#\s]*PROVIDED[\#\s]*.*AS[\#\s]*IS.*[\#\s]*AND[\#\s]*THE[\#\s]*AUTHOR[\#\s]*DISCLAIMS[\#\s]*ALL[\#\s]*WARRANTIES[\#\s]*WITH[\#\s]*REGARD[\#\s]*TO[\#\s]*THIS[\#\s]*SOFTWARE[\#\s]*INCLUDING[\#\s]*ALL[\#\s]*IMPLIED[\#\s]*WARRANTIES[\#\s]*OF[\#\s]*MERCHANTABILITY[\#\s]*AND[\#\s]*FITNESS.[\#\s]*IN[\#\s]*NO[\#\s]*EVENT[\#\s]*SHALL[\#\s]*THE[\#\s]*AUTHOR[\#\s]*BE[\#\s]*LIABLE[\#\s]*FOR[\#\s]*ANY[\#\s]*SPECIAL,[\#\s]*DIRECT,[\#\s]*INDIRECT,[\#\s]*OR[\#\s]*CONSEQUENTIAL[\#\s]*DAMAGES[\#\s]*OR[\#\s]*ANY[\#\s]*DAMAGES[\#\s]*WHATSOEVER[\#\s]*RESULTING[\#\s]*FROM[\#\s]*LOSS[\#\s]*OF[\#\s]*USE,[\#\s]*DATA[\#\s]*OR[\#\s]*PROFITS,[\#\s]*WHETHER[\#\s]*IN[\#\s]*AN[\#\s]*ACTION[\#\s]*OF[\#\s]*CONTRACT,[\#\s]*NEGLIGENCE[\#\s]*OR[\#\s]*OTHER[\#\s]*TORTIOUS[\#\s]*ACTION,[\#\s]*ARISING[\#\s]*OUT[\#\s]*OF[\#\s]*OR[\#\s]*IN[\#\s]*CONNECTION[\#\s]*WITH[\#\s]*THE[\#\s]*USE[\#\s]*OR[\#\s]*PERFORMANCE[\#\s]*OF[\#\s]*THIS[\#\s]*SOFTWARE.\s(\#* *\n)*|\1 SPDX-License-Identifier: ISC\n\n|s' $(cat filelist)

perl -i -p0e 's|\/\*[*\s]*Redistribution[*\s]*and[*\s]*use[*\s]*in[*\s]*source[*\s]*and[*\s]*binary[*\s]*forms,[*\s]*with[*\s]*or[*\s]*without[*\s]*modification,[*\s]*are[*\s]*permitted[*\s]*provided[*\s]*that[*\s]*the[*\s]*following[*\s]*conditions[*\s]*are[*\s]*met:[*\s]*[1. ]*Redistributions[*\s]*of[*\s]*source[*\s]*code[*\s]*must[*\s]*retain[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice,[*\s]*this[*\s]*list[*\s]*of[*\s]*conditions[*\s]*and[*\s]*the[*\s]*following[*\s]*disclaimer.[*\s]*[*\s]*[2. ]*Redistributions[*\s]*in[*\s]*binary[*\s]*form[*\s]*must[*\s]*reproduce[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice,[*\s]*this[*\s]*list[*\s]*of[*\s]*conditions[*\s]*and[*\s]*the[*\s]*following[*\s]*disclaimer[*\s]*in[*\s]*the[*\s]*documentation[*\s]*and.or[*\s]*other[*\s]*materials[*\s]*provided[*\s]*with[*\s]*the[*\s]*distribution.[*\s]*[3. ]*.*used[*\s]*to[*\s]*endorse[*\s]*or[*\s]*promote[*\s]*products[*\s]*derived[*\s]*from[*\s]*this[*\s]*software[*\s]*without[*\s]*specific[*\s]*prior[*\s]*written[*\s]*permission.[*\s]*THIS[*\s]*SOFTWARE[*\s]*IS[*\s]*PROVIDED.*AS[*\s]*IS.*[*\s]*AND[*\s]*ANY[*\s]*EXPRESS[*\s]*OR[*\s]*IMPLIED[*\s]*WARRANTIES,[*\s]*INCLUDING,[*\s]*BUT[*\s]*NOT[*\s]*LIMITED[*\s]*TO,[*\s]*THE[*\s]*IMPLIED[*\s]*WARRANTIES[*\s]*OF[*\s]*MERCHANTABILITY.*FITNESS[*\s]*FOR[*\s]*A[*\s]*PARTICULAR[*\s]*PURPOSE.*ARE[*\s]*DISCLAIMED.[*\s]*IN[*\s]*NO[*\s]*EVENT[*\s]*SHALL.*LIABLE[*\s]*FOR[*\s]*ANY[*\s]*DIRECT,[*\s]*INDIRECT,[*\s]*INCIDENTAL,[*\s]*SPECIAL,[*\s]*EXEMPLARY,[*\s]*OR[*\s]*CONSEQUENTIAL[*\s]*DAMAGES[*\s]*.INCLUDING,[*\s]*BUT[*\s]*NOT[*\s]*LIMITED[*\s]*TO,[*\s]*PROCUREMENT[*\s]*OF[*\s]*SUBSTITUTE[*\s]*GOODS[*\s]*OR[*\s]*SERVICES;[*\s]*LOSS[*\s]*OF[*\s]*USE,[*\s]*DATA,[*\s]*OR[*\s]*PROFITS;[*\s]*OR[*\s]*BUSINESS[*\s]*INTERRUPTION.[*\s]*HOWEVER[*\s]*CAUSED[*\s]*AND[*\s]*ON[*\s]*ANY[*\s]*THEORY[*\s]*OF[*\s]*LIABILITY,[*\s]*WHETHER[*\s]*IN[*\s]*CONTRACT,[*\s]*STRICT[*\s]*LIABILITY,[*\s]*OR[*\s]*TORT[*\s]*.INCLUDING[*\s]*NEGLIGENCE[*\s]*OR[*\s]*OTHERWISE.[*\s]*ARISING[*\s]*IN[*\s]*ANY[*\s]*WAY[*\s]*OUT[*\s]*OF[*\s]*THE[*\s]*USE[*\s]*OF[*\s]*THIS[*\s]*SOFTWARE,[*\s]*EVEN[*\s]*IF[*\s]*ADVISED[*\s]*OF[*\s]*THE[*\s]*POSSIBILITY[*\s]*OF[*\s]*SUCH[*\s]*DAMAGE.[*\s]*\*\/|/* SPDX-License-Identifier: BSD-3-Clause */|s' $(cat filelist) $1

perl -i -p0e 's|(\#\#*) *Redistribution[\#\s]*and[\#\s]*use[\#\s]*in[\#\s]*source[\#\s]*and[\#\s]*binary[\#\s]*forms,[\#\s]*with[\#\s]*or[\#\s]*without[\#\s]*modification,[\#\s]*are[\#\s]*permitted[\#\s]*provided[\#\s]*that[\#\s]*the[\#\s]*following[\#\s]*conditions[\#\s]*are[\#\s]*met:[\#\s]*[*1. ]*Redistributions[\#\s]*of[\#\s]*source[\#\s]*code[\#\s]*must[\#\s]*retain[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice,[\#\s]*this[\#\s]*list[\#\s]*of[\#\s]*conditions[\#\s]*and[\#\s]*the[\#\s]*following[\#\s]*disclaimer.[\#\s]*[*2. ]*Redistributions[\#\s]*in[\#\s]*binary[\#\s]*form[\#\s]*must[\#\s]*reproduce[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice,[\#\s]*this[\#\s]*list[\#\s]*of[\#\s]*conditions[\#\s]*and[\#\s]*the[\#\s]*following[\#\s]*disclaimer[\#\s]*in[\#\s]*the[\#\s]*documentation[\#\s]*and.or[\#\s]*other[\#\s]*materials[\#\s]*provided[\#\s]*with[\#\s]*the[\#\s]*distribution.[\#\s]*[\#\s]*[*3. ]*.*used[\#\s]*to[\#\s]*endorse[\#\s]*or[\#\s]*promote[\#\s]*products[\#\s]*derived[\#\s]*from[\#\s]*this[\#\s]*software[\#\s]*without[\#\s]*specific[\#\s]*prior[\#\s]*written[\#\s]*permission.[\#\s]*THIS[\#\s]*SOFTWARE[\#\s]*IS[\#\s]*PROVIDED.*AS[\#\s]*IS.*[\#\s]*AND[\#\s]*ANY[\#\s]*EXPRESS[\#\s]*OR[\#\s]*IMPLIED[\#\s]*WARRANTIES,[\#\s]*INCLUDING,[\#\s]*BUT[\#\s]*NOT[\#\s]*LIMITED[\#\s]*TO,[\#\s]*THE[\#\s]*IMPLIED[\#\s]*WARRANTIES[\#\s]*OF[\#\s]*MERCHANTABILITY.*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.*ARE[\#\s]*DISCLAIMED.[\#\s]*IN[\#\s]*NO[\#\s]*EVENT[\#\s]*SHALL.*LIABLE[\#\s]*FOR[\#\s]*ANY[\#\s]*DIRECT,[\#\s]*INDIRECT,[\#\s]*INCIDENTAL,[\#\s]*SPECIAL,[\#\s]*EXEMPLARY,[\#\s]*OR[\#\s]*CONSEQUENTIAL[\#\s]*DAMAGES[\#\s]*.INCLUDING,[\#\s]*BUT[\#\s]*NOT[\#\s]*LIMITED[\#\s]*TO,[\#\s]*PROCUREMENT[\#\s]*OF[\#\s]*SUBSTITUTE[\#\s]*GOODS[\#\s]*OR[\#\s]*SERVICES;[\#\s]*LOSS[\#\s]*OF[\#\s]*USE,[\#\s]*DATA,[\#\s]*OR[\#\s]*PROFITS;[\#\s]*OR[\#\s]*BUSINESS[\#\s]*INTERRUPTION.[\#\s]*HOWEVER[\#\s]*CAUSED[\#\s]*AND[\#\s]*ON[\#\s]*ANY[\#\s]*THEORY[\#\s]*OF[\#\s]*LIABILITY,[\#\s]*WHETHER[\#\s]*IN[\#\s]*CONTRACT,[\#\s]*STRICT[\#\s]*LIABILITY,[\#\s]*OR[\#\s]*TORT[\#\s]*.INCLUDING[\#\s]*NEGLIGENCE[\#\s]*OR[\#\s]*OTHERWISE.[\#\s]*ARISING[\#\s]*IN[\#\s]*ANY[\#\s]*WAY[\#\s]*OUT[\#\s]*OF[\#\s]*THE[\#\s]*USE[\#\s]*OF[\#\s]*THIS[\#\s]*SOFTWARE,[\#\s]*EVEN[\#\s]*IF[\#\s]*ADVISED[\#\s]*OF[\#\s]*THE[\#\s]*POSSIBILITY[\#\s]*OF[\#\s]*SUCH[\#\s]*DAMAGE.\s(\#* *\n)*|\1 SPDX-License-Identifier: BSD-3-Clause\n\n|s' $(cat filelist)

Change-Id: I7ff9c503a2efe1017a4666baf0b1a758a04f5634
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11 17:12:16 +00:00
Patrick Georgi 6b5bc77c9b treewide: Remove "this file is part of" lines
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 17:11:40 +00:00
Patrick Georgi 7333a116b3 util/: Replace GPLv2 boiler plate with SPDX header
Used commands:
perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist)

perl -i -p0e 's|This[\s*]*program[\s*]*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.*[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist)

perl -i -p0e 's|\/\*[\s*]*.*This[\s*#]*program[\s*#]*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.*[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist)

perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)

perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)

Change-Id: I1008a63b804f355a916221ac994701d7584f60ff
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09 21:22:08 +00:00
Patrick Georgi ea063cb975 AUTHORS, util/: Drop individual copyright notices
We have the git history which is a more reliable librarian.

Change-Id: Idbcc5ceeb33804204e56d62491cb58146f7c9f37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2020-05-09 21:21:32 +00:00
Patrick Georgi 02363b5e46 treewide: Move "is part of the coreboot project" line in its own comment
That makes it easier to identify "license only" headers (because they
are now license only)

Script line used for that:
  perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...

Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06 22:20:28 +00:00
Rob Barnes 18fd26cb08 amdfwtool: Allow for up to 16 APCB entries
Increase the number of allowed APCB entries in amdfwtool.

BUG=b:150455865
TEST=Boot Trembyle
BRANCH=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ibdd2f2b9766735bc9aba98b5216e589b6cace238
Reviewed-on: https://chromium-review.googlesource.com/2084944
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39861
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-27 22:52:48 +00:00
Eric Peers af505671a1 util/amdfwtool: Fix file open error msg
Print out the name of the file that failed to open.

BUG=none
TEST=rerun build-board.sh with missing files
BRANCH=none

Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb
Reviewed-on: https://chromium-review.googlesource.com/2090667
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-17 22:49:09 +00:00
Marshall Dawson c4a8c48b2f util/amdfwtool: Clarify APOB NV requirements
Relocate the first size check.  This was automatically continuing
and not looking for the caller incorrectly passing a destination.

New information indicates that the APOB_NV should always be present
in the system.  Augment the missing size check to inferring whether
a missing size is valid, as in the case of older products, or truly
missing when it's needed.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-02 16:35:51 +00:00
Patrick Georgi 900a254475 util/amdfwtool: Improve comment's grammar
Change-Id: I2daa57c1982346e48dbd91a94864baf2f11c2129
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-18 15:33:43 +00:00
Elyes HAOUAS 99e54fece3 util: Fix typos
Change-Id: Ia405384211aa53ac089a99ecd31acc25effdb71e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17 15:53:49 +00:00
Idwer Vollering a682fc81ae util/amdfwtool: guard typedef aliases
Build tested on Ubuntu 18 LTS, FreeBSD.

Change-Id: Ida2c1f36aba7469d69dbb12ee6afce4a181bd6b7
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20 14:43:31 +00:00
Marshall Dawson 2dd3b5c0f8 util/amdfwtool: Add instances for APCB backup
Match each of the possible APCB items with a corresponding backup APCB.
A missing backup copy can prevent the system from booting.

Change-Id: I400194b2763239896214ea42cfe6fbeb8ed261a8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-06 23:27:36 +00:00
Marshall Dawson 0581bf6a75 util/amdfwtool: Add holding locations for more APCBs
Increase the number of potential APCB images to 5 by adding to the
amd_bios_table.  New instance IDs are from 0 to 4.  The backup APCB
block (type 0x68) still supports only instance ID 0.

Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20 22:09:47 +00:00
Marshall Dawson 94f249254f util/amdfwtool: Grow the Embedded Firmware Structure
Ensure adequate space exists for all Embedded Firmware Structure
fields.

Field definitions are NDA only.  See PID #55758 "AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors".

BUG=b:141790457
TEST=run on Mandolin

Change-Id: I098ffc7c05d27387a877e6b7c8628d98939bd9af
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35667
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-16 02:29:07 +00:00
Marshall Dawson b85ddc5d44 util/amdfwtool: Correct fletcher32 algorithm
Change the fletcher32 checksum calculation to match PSP and AGESA
implementations.

The symptom of the failure has only been noted in Picasso's BIOS
Directory Table, when a BIOS binary image of different sizes were
passed to amdfwtool.  The PSP halts the boot process with the bad
BDT checksum, and if allowed to continue, AGESA asserts later due
to a failed BDT verification.

This version has been verified to produce the same result as found
at https://en.wikipedia.org/wiki/Fletcher%27s_checksum.

TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom
     is unchanged.

Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-29 05:58:08 +00:00
Martin Roth d3ce8c8442 util/amdfwtool: Add option to build verstage binary into the PSP
For AMD's Family17h processors, verstage needs to be run in the PSP,
before memory is initialized.  This adds that binary into the PSP
directory.

See the Family17h documentation in the coreboot documentation directory
for more information.

BUG=b:137338769
TEST=Build, add test binary to mandolin board, boot

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-15 17:47:04 +00:00
Martin Roth ec933135ce util/amdfwtool: Do misc cleanup
- Correct command line argument for microcode patches from -u to -O
- Add #if PSP_COMBO around new_combo_dir() as it's only called when
that's enabled.
- Remove unused variable in integrate_bios_firmwares()
- Correct enum type from amd_fw_type to amd_bios_type in
register_fw_addr()

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-15 17:46:46 +00:00
Jacob Garber 967f862e47 util/amdfwtool: Close file descriptor on error
Prevents a resource leak.

Change-Id: Id5da2df3e37cba499cd2e9a7c3ede34e4de2ed77
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 18:21:41 +00:00
Marshall Dawson ce2b2bad77 util/amdfwtool: Update for Family 17h
Add arguments for additional PSP blobs needed with Family 17h support,
including the new AGESA binary loaders.

Create a new type of structure and entry for a BIOS directory table,
containing PMU code, microcode updates, as well as the BIOS initial
code.

Details on each of these items may be found in the AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors
(NDA only, #55758).

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-19 19:14:39 +00:00
Marshall Dawson 24f73d4f53 util/amdfwtool: Add multilevel PSP directory table
Add the ability to generate two PSP directory table levels.  The PSP
is capable of supporting two levels, with the primary intended to
remain pristine for the life of the system, and the second updatable.
In the event the second becomes corrupted, the primary is still
sufficient to allow a recovery of the other.

This patch modifies no directory table structures currently in use.
The soc or southbridge must pass an argument to force building the
secondary table.

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13 18:01:07 +00:00
Marshall Dawson 7c1e1428ad util/amdfwtool: Align PSP NVRAM
Align the PSP's NVRAM item since it's intended to be updateable
in the flash device.

Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13 18:00:27 +00:00
Marshall Dawson ef79fccf4e util/amdfwtool: Add argument for soft fuse override
Allow the soc build to pass a soft fuse value to the utility.  This
helps maintain compatibility across PSP generations.

Add a generic 'other' item to the amd_fw_entry structure that may
be used by non-fuse entries in the future.

TEST=Verify google/grunt amdfw.rom unchanged before and after.
     Compare internal board using override before and after.

Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-13 18:00:05 +00:00
Marshall Dawson 02bd77379b util/amdfwtool: Allow 0-length blobs
A side effect of the change 8e0dca05
"util/amdfwtool: Add generic image copy function"
was to treat a read operation of zero bytes as a failure.  Some
implementations exist that use zero length files as a means of
removing functionality.  This causes amdfwtool to exit with an
error.

Put the zero length capability back in, and generate the requested
table entry with a length field of 0x0.

TEST=Boot google/grunt, inspect PSP directory table
BUG=b:128507639

Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 12:57:57 +00:00
Marshall Dawson 67bbb6db41 util/amdfwtool: Remove fanless SMU options
Complete the removal of the fanless command line options.  The only soc
using them has been converted to use the subprogram option instead.

TEST=Verify amdfw.rom is unchanged before and after the conversion
BUG=b:126691068

Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:03:59 +00:00
Marshall Dawson dbae632fec util/amdfwtool: Split type field for PSP entries
Separate the type field for the PSP directory table to better match the
AMD Platform Security Processor BIOS Architecture Guide (order #55758,
NDA only).  Instead of a 32-bit type, change to an 8-bit value and an
8-bit subprogram field to allow for a more generic application across
family/model products.

This patch also eliminates the "fanless" types, previously added for
stoneyridge, and converts the --smufnfirmware and --smufnfirmware2
arguments to use a subprogram value of 1.

Subsequent patches will change the stoneyridge makefile to use the
new option, and eliminate the fanless arguments.

TEST=Boot google/grunt, confirm no difference in amdfw.rom file.
BUG=b:126691068

Change-Id: If8f33000c31cba21f286f54459de185c21e46268
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:03:07 +00:00
Marshall Dawson 2794a86b1b util/amdfwtool: Streamline functions with context
Replace variables and function arguments with a context that may be
maintained and passed.  Add macros to clarify the pointer math.  Add
functions to generate tables instead of relying on correct ordering
and math.  Use defined sizes for tables instead of arbitrary additions
to an index.

TEST=Verify no difference in amdfw.rom for google/grunt before and
     after, and verify a grunt build with PSP_COMBO=1 runs.

Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:02:49 +00:00
Marshall Dawson 8e0dca05fb util/amdfwtool: Add generic image copy function
Consolidate the code that opens, stats, copies, and closes the
individual files into a single function.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied

Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:02:25 +00:00
Marshall Dawson a378c22f77 util/amdfwtool: Combine table header population
Rename psp_fill_head() and call it with the cookie to populate the
header.  The combo header and PSP directory header are similar and
should be calculated the same way.

Change-Id: I7e634542de65576addadbe683596cbe572de3dcd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:02:10 +00:00
Marshall Dawson 0e02ce83a1 util/amdfwtool: Remove duplicate PSP2 support
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed.  Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.

This patch is part 2 of 2 to reduce the number of command-line options
to amdfwtool.  Part 1 added the --combo-capable option that helps
put the PSP directory pointer in the correct location.  Part 2
removes the duplicated table, the support code, options, and updates
the usage text.

TEST=Build before/after images for grunt, bettong, apu2, and diff
     hexdumps of the amdfw.rom files.  Built/ran grunt with PSP_COMBO
     defined as 1.
BUG=b:126691068

Change-Id: I542a7f5023137f30fbe00533452d4448117df487
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:01:40 +00:00
Marshall Dawson 67d868d04b util/amdfwtool: Introduce combo-capable option
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed.  Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.

This patch is part 1 of 2 to reduce the number of command-line options
to amdfwtool.  Create a new option that is used as an indicator for
which Embedded Firmware offset to use.  Part 2 will be added once
makefiles no longer use the duplicated options.

This patch also adds two new options for fanless SMU firmware to be
used instead of the ones that will be removed in part 2.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied
BUG=b:126691068

Change-Id: I249700c6addad1c0ecb495a406ffe7a022dd920b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:01:03 +00:00
Marshall Dawson 8a45a4dc3f util/amdfwtool: Clarify call to fletcher32
The fletcher32 algorithm generates a sum over a range of 16-bit
WORDs.  Change the function's interface to be more generic,
accepting a more intuitive size in BYTEs.  Don't require the
caller to understand the nature of the algorithm and convert to
WORDs prior to calling.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied

Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:00:30 +00:00
Marshall Dawson 239286ca44 util/amdfwtool: Clarify calculations with structures
Replace the use of multiples of DWORDs with structures that
describe the Embedded Firmware Table, and PSP directory
headers & entries.

TEST=Verify no difference in amdfw.rom for google/grunt build
     (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh),
     and pcengines/apu2 (F16h 30h-3Fh).  PSP_COMBO builds but
     was not verified.

Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:00:17 +00:00
Marshall Dawson c38c0c91aa util/amdfwtool: Fix iteration of PSP firmwares
Correct an oversight in the utility that attempts to match up eligible
PSP directory table entries with blob names passed on the command
line.  A 1:1 matchup of items shouldn't be assumed, so the i iterator
shouldn't be used to walk both lists.

This change has no effect on google/grunt (Family 15h Models 70h-7Fh),
but eliminates blank entries of all FF's on builds of amd/bettong
(F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh).  Removal of entries
also affects the checksum accordingly.

TEST=Build before/after images for grunt, bettong, apu2, and diff
     hexdumps of the amdfw.rom files

Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 15:58:42 +00:00
Tom Hiller 8ba9e8cf63 util: Add description.md to each util
Descriptions are taken from the files themselves or READMEs. Description
followed by a space with the language in marked up as code.

Change-Id: I5f91e85d1034736289aedf27de00df00db3ff19c
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-26 13:26:50 +00:00
Richard Spiegel 7b89a28149 util/amdfwtool/amdfwtool.c: Check fstat return
Funtion fstat will return -1 if there's any error, 0 if successful.
Check that fstat return is equal to 0, print error message and exit if
not 0.

This fixes CIDs 1353018 and 1353020

BUG=b:72062481
TEST=Build no errors

Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 09:59:40 +00:00
Richard Spiegel 137484dee7 util/amdfwtool/amdfwtool.c: Verify it actually read bytes
The function read() returns the number of bytes actually read. Program is
assuming it actually read the required number of bytes without checking.
This is wrong.

This fixes CIDs 1353019 and 1353021

BUG=b:72062481
TEST=Build no errors

Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24 16:24:29 +00:00
Richard Spiegel bff4545ccf util/amdfwtool/amdfwtool.c: Check for negative return
File open function <open()> will return -1 if there's any error. Check that
the return is greater or equal to 0 before using fstat(). Print error message
and exit if there's an error.

This fixes CIDs 1353018, 1353020, 1353027 and 1353028

BUG=b:72062481
TEST=Build no errors

Change-Id: I77d6973d1ad1eadb93922866e618038045be5937
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23 20:10:52 +00:00
Martin Roth 0d3b11898b util/amdfwtool: Add option for directory location
The AMD firmware directory can go in a number of different locations.
This patch allows amdfwtool to write the directory correctly for those
different locations.

If the --location switch is not added to the command line, the default
location at ROM base address + 0x20000 is used as before.

BUG=b:65484600
TEST=Set PSP firmware location, compare amdfw.rom to previously built
version.  Verify new location pointers.

Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05 02:49:09 +00:00
Marc Jones d81250cebc amdfwtool: Move normal firmware 2 after fanless firmware2s
Move the images around in the image stitching. This addresses
an issue found with PSP firmware loading on the Google Kahlee
mainboard.

Note firmware1 must come before firmware2 in the image or
the PSP will not allow APU to execute.

Change-Id: I85963fa93d6efd707cedfbc04b92d302ad5de3b1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19170
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27 23:27:06 +02:00
Marshall Dawson f4b9b41c47 util/amdfwtool: Add fanless SMU firmware options
The Stoney Ridge program has OPNs that are considered fanless.  These
APUs are strapped to search for unique SMU firmware, indicated by
Type[8]=1 in the directory table entry.

Add new options to amdfwtool and include the blobs in the build with
the appropriate bit set in the Type encoding.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da)

Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18991
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28 22:26:19 +02:00
Martin Roth 8955d5572f util/amdfwtool: Wrap long lines, excluding comments
Change-Id: I35c4340cf14ca1609ce3bfcac78cc4e286eff34a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17326
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-21 23:37:08 +01:00
Martin Roth cd15bc86f1 util/amdfwtool: Fix whitespace
Change-Id: I33e41b745e7ec55ed39d7125fc74b1619d28bb54
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17325
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-21 23:36:49 +01:00
Martin Roth 31d95a2eb2 util/amdfwtool: unify return values, verify the file open
- Return an error if the specified file could not be opened. To do this
cleanly, the return value was added.
- Since there's now a unified return value, use it where it makes sense.
- Don't return an error from --help.  If you've asked for usage, it's
not an error.

Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17324
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:26:45 +01:00
Martin Roth 0e94062c2b util/amdfwtool: add usage text
Change-Id: I0ddb4516c03b0240d9134b35753ad901932d3f53
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17323
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:26:06 +01:00
Martin Roth 8806f7f662 util/amdfwtool: fix clang warnings
Various fixes for clang warnings:

warning: arithmetic on a pointer to void is a GNU extension
- change *rom from void* to char* and cast back to void* as needed

warning: implicit conversion changes signedness
- In ALIGN macro, pass in value as unsigned

warning: no previous prototype for function
- Change functions to static

warning: no previous extern declaration for non-static variable
- Change global variables to static

warning: comparison of integers of different signs
- Make loop variable 'i' unsigned

warning: variable 'output' may be uninitialized
- Make sure an output filename was specified

warning: implicit conversion loses integer precision
- cast fd_stat.st_size to the appropriate type

Change-Id: I0134a79c00938e121e63b52fd63bd502f4cb9e99
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17322
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:25:45 +01:00
Martin Roth 60f1551461 util/amdfwtool: Update with ROM size command line parameter
Previously, the ROM size was passed into amdfwtool solely as a #define,
meaning that all boards built with the tool would assume the same size
ROM.  This became a problem when the default rom for abuild was updated
to be a board with a 256KB ROM.

The temporary solution was to build amdfwtool individually for each
board that needed it.  This replaces that workaround by allowing the
ROM size to be passed in as a command line parameter.

- Add the -f | --flashsize option to accept a hex value for the ROM
size.
- Add checks to make sure the ROM size supplied is large enough.
- Because the ROM size is not hardcoded, it needs to be passed to
various functions.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615
Reviewed-on: https://review.coreboot.org/17321
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:24:46 +01:00
Marc Jones 350630aefb util/amdfwtool: Increase space used for structures
Double the space for psp2dir to 0x200.

Based on advice from AMD, increase the region containing
the signature to 4K.

Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639)

Change-Id: If60132f913928bab0c2fe4aacedf342080929599
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17148
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02 18:39:53 +01:00
Marc Jones 90099b6803 util/amdfwtool: Add PSP2 options to optstring
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de)

Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17147
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02 18:39:42 +01:00
Marshall Dawson e7d892c651 util/amdfwtool: Fix duplicate long option name
Make the PSP2 smufirmware2 name unique so the command-line option
gets picked up.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: <marcj303@gmail.com>
(cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624)

Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17146
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02 18:39:29 +01:00
zbao c3a08a9d5e amdfwtool: Fix some PSP2 issues
1. Change the function which integrated one firmware, to the function
   which pushes the whole group. Use fw_table as a parameter instead
   of using the global table name.
2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2
   can exist without PSP1. For some APU, the PSP directory has to be
   put in PSP2 field (ROMSIG 0x14).
3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It
   is tested, and it is true.

These above changes are overlapping, hard to split them. Sorry.

Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13808
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03 12:03:03 +01:00
zbao c3b0b72813 amdfwtool: Postpone the usage of PSP combo directory
If we only need to "combo" two PSP directories into one image,
we can put first address in romsig 0x10 and second one in
romsig 0x14.

If we really need to put three, the 0x14 is the combo directory
which points to multiple level-2 PSP directories.

I guess that two PSP can also use combo directory, with only
one level-2 directory. But nobody seems to do that.

Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-20 04:57:42 +01:00
zbao 6e2f3d1df4 amdfwtool: Fix some fields in PSP level-2 directory
Change-Id: Ib2da7f2210a823fce7f05824e2a2b73d3c0490e9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13738
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-20 04:57:20 +01:00
zbao 85f362e9b6 amdfwtool: Fill the first 3 romsig entries as 0
I didn't go back through the development guide for this.
But based on test, if the empty entry is filled as 0xFFFFFFFF,
instead of 0, the USB3 port can not be used.

Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant
with the case before the amdfwtool is used.

Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12665
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08 03:45:11 +01:00
Zheng Bao 4fcc9f2e54 amdfwtool: Correct the PSP2 directory layout
PSP2 is for Combo BIOS, which is the idea that one image supports 2
kinds of APU.

The PSP2 feature is for the future, not for current products.
The newest document about PSP2 is not available. I made it from the
draft code I made when I was in AMD.

Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12474
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26 07:11:22 +01:00
Zheng Bao 9c7ff7bc15 amdfwtool: Add amdfwtool to combine AMD firmwares
Combine all needed AMD firmware into one single firmware, which going to
be added as one single CBFS module.

Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12419
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19 04:11:59 +01:00