For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1
to set SPD for index 4. This change adds a helper macro to translate
DDR4 channel # to the index # that the FSP expects.
BUG=b:154445630
TEST=Verified that memory initialization for DDR4 is successful.
Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Assuming given system is populated with multiple CPUs of same SKUs,
calculate number of threads based on MAX_SOCKET.
This is a stop gap solution until proper way of identifying total
number of sockets is determined.
Change-Id: I7ebad3d57c47b9eeb7d727ffb21bc0a1a84734fd
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Currently FSP-M does not implement the spec completely, e.g it is unable
to use user-provided heap location in CAR. While this is being resolved,
this workaround is a stop-gap solution that allows multi-socket usage.
TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB
Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need to allow motherboards to configure certain parameters that
are specific to it. Hence, invoke this function. Also, provide a
weak motherboard implementation that does nothing.
Change-Id: Ifa2824811273236a66e742404856fbe17d4cf496
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40552
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's supposed to be selected by default on devices that ship with the
device, while there's little need to add it on other devices.
Change-Id: I57badee9ce1e8a3c8df313953aba02cc3489ff97
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40660
Reviewed-by: Michael Niewöhner
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's supposed to be selected by default on devices that ship with the
device, while there's little need to add it on other devices.
Change-Id: I2747c4f825601b2fbffc908821035e4f66c5a3b8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1) Allows MKBP events from the EC to wake the system from suspend states.
2) Remove EC_HOST_EVENT_MKBP from the EC_SCI_EVENTS mask, so that MKBP
events don't generate an SCI. The EC is also being changed to use host
events to wake up the system, and use the EC_INT_L line for MKBP IRQ
signalling. Otherwise, there would be two IRQs generated for MKBP events.
BUG=b:148976961
BRANCH=firmware-hatch-12672.B
TEST=Verify MKBP events wake system
TEST=Verify MKBP IRQs are run
Change-Id: I8420a996cb1975007cbbbefe9e2f8f1fca91b666
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
I2C0&1 are either not available or not functional. Add place holders
instead, so that the array index matches the I2C controller number. I2C4
is slave device only, so do not initialize it as I2C host controller.
Also do some slight refactoring.
BUG=b:153152871
BUG=b:153675916
Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1897071
Reviewed-on: https://chromium-review.googlesource.com/2057468
Reviewed-on: https://chromium-review.googlesource.com/2094855
Reviewed-on: https://chromium-review.googlesource.com/2149870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The device is always there, the Chromium OS configs always enable it,
so let's mirror that here for a better out of the box experience.
Change-Id: Ia2073ee7ecbdb37473e1f1002bc9ae0f7df58e42
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40657
Reviewed-by: Michael Niewöhner
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The device is always there, the Chromium OS config always enables it,
so let's mirror that here for a better out of the box experience.
Change-Id: Ic43a314aaed635ae2943df02abc5d163cc3c4ffd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40658
Reviewed-by: Michael Niewöhner
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch USB2 port1 and port3 for duffy and kaisa due to circuit change.
BUG=b:153682207, b:154451230, b:154445635
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
boot on puff board
Change-Id: I9c0cbcbefd045085fb70cf4f41869ab9b98103c4
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the
appropriate calling stage (bootblock or romstage). This means that
ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE
are 1. This keeps tripping up people who are just trying to write a
simple "are we in verstage (i.e. wherever the vboot init logic runs)"
check, e.g. for TPM init functions which may run in "verstage" or
ramstage depending on whether vboot is enabled. Those checks will not
work as intended for CONFIG_SEPARATE_VERSTAGE=n.
This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to
clarify that this macro can really only be used to check whether code is
running in a *separate* verstage, and clue people in that they may need
to cover the linked-in verstage case as well.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch restores the permission check for the kernel space which
was dropped when read_space_kernel was moved from Depthcharge by
CL:2155429.
BUG=chromium:1045217, chromium:1020578
BRANCH=none
TEST=none
Signed-off-by: dnojiri <dnojiri@chromium.org>
Change-Id: If6d487940f39865cadc0ca9d5de6e055ad3e017d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40579
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Romstage is now where software sync is performed for chromebooks.
EFS2 has been ported to romstage from Depthcharge. Puff should
follow.
This patch enables CONFIG_EARLY_EC_SYNC and disables
CONFIG_VBOOT_EC_EFS. EFS2 will be done in romstage.
BUG=b:147298634, chromium:1045217
BRANCH=none
TEST=Verify software sync succeeds on Puff.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I8d7c25f8281496c7adb282f5d4e0fc192d746e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40390
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 46ff62c3:
vboot: stop reading from ACPI for wpsw_boot
to commit id 55154620:
vboot: Add screens for recovery using disk
This brings in 37 new commits.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ie184cbe6cc18cea540966d5801472ae821ea3e86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40503
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a helper function dev_find_matching_device_on_bus()
which scans all the child devices on the given bus and calls a
match function provided by the caller. It returns the first device
that the match function returns true for, else NULL if no such device
is found.
Change-Id: I2e3332c0a175ab995c523f078f29a9f498f17931
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40543
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables support for generating ACPI nodes for I2C tunnel for
any GOOG0012 device that is sitting behind the Chrome EC. It accepts a
config "remote_bus" which allows mainboard to configure the id of the
remote bus that is being tunneled.
BUG=b:154290952
BRANCH=None
TEST=Verified that SSDT node for I2C tunnel behind Chrome EC is
generated correctly.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icfc0ec3725d7f1d20bcb5cb43a0a23aac72bf4eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add keymaps for keys that are not present in US keyboards.
Change-Id: I1ad4c483e81438456533b4c071a4a56cbee88f9c
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds scan_static_bus() as .scan_bus() callback for Chrome EC
device which allows scanning of devices sitting behind the EC using
the topology provided by mainboard's devicetree.cb.
BUG=b:154290952
TEST=Verified with follow-up changes that devices behind EC are scanned
correctly.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id3630db56774fba1e3fc53bf349588c4c585773b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40514
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In ACPI tables, Chrome EC device (CREC - HID GOOG0004) is a child of
EC device (EC0 - HID PNP0C09). However, in coreboot device tree, there
is no separate chip/device for EC0. Thus, acpi_name() needs to return
EC0.CREC as the ACPI name for the Chrome EC device. By returning the
ACPI name as EC0.CREC, all devices that live under Chrome EC device
can simply call acpi_device_path()/acpi_device_scope() to emit the
right path/scope.
In the future, if we ever add a special chip driver for handling EC0
(HID PNP0C09), then the ACPI name for Chrome EC can be fixed to return
CREC.
BUG=b:154290952
TEST=Verified that acpi_device_path()/acpi_device_scope() return the
correct name for Chrome EC device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Iec4b0226d1e98ddeb0f8ed8b89477fc4f453d221
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40513
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change checks to ensure that device/path passed into any of the
functions in device_const.c is not NULL. Since NULL is not expected to
be passed into these functions, this change adds a die() call in case
the assumption is broken.
Change-Id: I1ad8d2bcb9d0546104c5e065af1eeff331cdf96d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The EDID and command sequence are from BOE, the vendor.
BUG=b:148997748
TEST=Boots on Chromebook Kakadu and displayed developer firmware screen successfully.
Change-Id: Ieb510cb28882afc5b8023c2a57b31187e4a09fbd
Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40396
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are microcodes in .inc format out in the wild which contains
lines with just a comment. So these files look like the following
example:
; External header
dd 000000001h
dd 00000001bh
...
; Data
dd 000000000h
...
The lines with just a comment starts with a ';' and will break
the current awk formatting which is performed to reformat the content
into C code style. As we are just interested in the data we can simply
drop all lines that start with a ';' which sed can do pretty easy.
Change-Id: I9ff5db51667672cffd9d776fb9497962b4a6083a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The double quotes around the remaining shell parameters '${@:2}' causes
that the provided *.h files in $(CONFIG_CPU_MICROCODE_HEADER_FILES),
which is a space separated list, cannot be broken down to every single
file as needed but stay as a single parameter in the for-loop.
Therefore, the called function 'include_file' will get a single
parameter with all files which will lead to a broken C code in
terms of a wrong #include-syntax. This causes the script to fail.
To fix this remove the double quotes which works just fine.
Change-Id: Iab7b0dc8d850973d6af764899907d383e9ec7743
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Newly added code in commit CB:25546 contains spaces instead of TABs for
line indent. Replace every 4 spaces by a single TAB to match our coding
guides.
Change-Id: Ie3633bb42643f4abb5f1a8827a7dc2c9e023d6aa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some PCI peripherals, such as discrete VGA adapters, require a great
amount of memory mapped IO. This patch allows the user to select at
build time the bottom IO to leave enough space for such devices.
We cannot calculate this value at runtime because it has to be set
before the PCI devices are enumerated. 0x80000000 has been successfully
boot-tested on A88XM-E (fam15tn), G505S (fam15tn) and AM1I-A (fam16kb).
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Jenkins does not build using .config.facebook_fbg1701 on new patches.
Rename the config file adding '.mboot_vboot'. Now FACEBOOK_FBG1701
and FACEBOOK_FBG1701_MBOOT_VBOOT are included in Jenkins test result.
BUG=N/A
TEST=Build and boot Facebook fbg1701
Change-Id: Ib54cc29e7ff34553c19fa3502872d6e7aee5fbe8
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40557
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
USB routing has changed on reference schematics after Puff rev1 has
built. This may confuse people trying to c&p devicetree from the Puff.
So add comment to clearly note that there was change, hopefully
preventing c&p errors.
BUG=b:153682207
BRANCH=None
TEST=None
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I5c43a5c04c81b6708c9eeabc48ef11961d7c8561
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40546
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMBus uses 7-bits address, change it from 8-bits to 7-bits.
BUG=b:151702387
TEST=Check Memory SPD data is correct in console log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1720b4d6aa0bc785ad86234b3523bb0676ec5c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Deltan will be using the integrated Intel GbE for LAN
functionality. Deltaur will not have a LAN port, and so does not need
the GbE region. This patch adds a new FMAP descriptor file which
explicitly supports the GbE region (chromeos-gbe.fmd), and removes the
GbE region from chromeos.fmd. Deltan is then assigned chromeos-gbe.fmd,
and Deltaur is assigned chromeos.fmd.
BUG=b:150165131
TEST=emerge-deltaur coreboot chromeos-bootimage
and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add Type-C subsystem power management support for RTD3.
BUG=b:140290596
TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build
with the firmware CM. Added acpi debug and booted to kernel. Probed
devices PM_STATE transition from D0 to D3 entry/exit while system at S0.
TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3, offset:0xA4, PM_STATE:D3HT.
xhci:00:0d.0, offset:0x74, PM_STATE:D0D3.
dma:00:0d.2/00.0d.3, offset:0x84, PM_STATE:PMST.
Verified xhci/dma/pcie root ports power runtime_status to be suspended and suspended
time tick through /sys/bus/pci/devices/bus:device:func/power.
Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The WDB (Write Data Buffer) is a data region in CAR, used as a
scratchpad in the read and write training algorithms of memory
initialization. Both SNB and IVB use this buffer, but HSW does not.
Unlike earlier chipsets, Haswell contains much more in-hardware memory
training machinery, known as REUT (Robust Electrical Unified Testing).
Among other changes, the REUT hardware has a pattern storage buffer,
which renders the need for a pattern storage buffer in CAR obsolete.
Deprecate the WDB-related parameters in the pei_data structure for
Haswell, as they are leftovers from the previous generation's MRC.
Remove them from the mainboards, and explain why they are not required.
Because the MRC ABI has to remain the same, the layout of pei_data must
not be changed, so rename the WDB parameters instead of deleting them.
Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf.
Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This implements the SPI driver for the QUP core.
Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36517
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This implements the UART driver in SoC
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/25373/78
Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35500
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The frequency to be used by UART client is 7.3728MHz, thus define it in
the clock header to be used by the driver.
Tested: UART frequency request by client driver.
Change-Id: I1ced350fe9826ea05b03ffc11aced2c21fe85c9e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable Wifi and Bluetooth for Jasper Lake RVP with following changes:
1. Enable related pci root ports for WLAN and BT
2. Disable unused root ports and clkreq for unused clocks
3. Configure GPIOs properly for M.2 port
BUG=None
BRANCH=None
TEST=Code compiles and able to detect Wifi/BT module on board.
Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
M.2 WWAN interface has GPIOs which requires coreboot to
configure all related GPIOs as per board schematics.
BUG=None
BRANCH=None
TEST=code compiles and WWAN device is detected in OS
Change-Id: I8ad978a619b50e16ad754177f1eb05cf7670b79f
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Each physical port should have the same group and position for both USB2
and USB3, but puff and its variants use different layout than the
baseboard so they must override PLD.
Ports are split into two groups for front and back, with positions in
each group numbered from left to right.
BUG=b:151579409
BRANCH=none
TEST=PLD_GroupToken and PLD_GroupPosition are set as expected in SSDT.
Change-Id: Ibe19e4faa1fbc7117687d789e9bd5584852a48c0
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Furquan Shaikh