Commit Graph

48036 Commits

Author SHA1 Message Date
Won Chung 18c2720c7f mb/google/brya/var/brask: Add ACPI _PLD custom values
This patch uses ACPI _PLD macros to add custom values for USB ports.

    C2  C0    A3  A2
   +----------------+
   |      REAR      |
   |                |
   |                |
   |                |
   |      FRONT     |
   +----------------+
       C1  A1  A0

BUG=b:232298007
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B

Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I6a9ead24ef9d73bc0b09301cf641009ced0c6810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64732
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08 22:03:56 +00:00
Paul Menzel 970554f90d vc/amd/agesa/f15tn: Declare `value` as constant in `GnbRegisterWriteTNDump()`
Do not discard the const qualifier in `GnbRegisterWriteTNDump()` to fix
the compiler warning below.

        CC         libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.o
    In file included from src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:53:
    src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: In function 'GnbRegisterWriteTN':
    src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:836:57: error: passing argument 3 of 'GnbRegisterWriteTNDump' discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
      836 |     GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value);
          |                                                         ^~~~~
    src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h:68:35: note: in definition of macro 'GNB_DEBUG_CODE'
       68 |     #define  GNB_DEBUG_CODE(Code) Code
          |                                   ^~~~
    src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:86:33: note: expected 'VOID *' {aka 'void *'} but argument is of type 'const VOID *' {aka 'const void *'}
       86 |   IN       VOID                *Value
          |            ~~~~~~~~~~~~~~~~~~~~~^~~~~
        CC         libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.o
        CC         libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.o
        CC         libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.o
        CC         libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.o
        CC         libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.o
    src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: At top level:
    cc1: note: unrecognized command-line option '-Wno-pragma-pack' may have been intended to silence earlier diagnostics
    cc1: all warnings being treated as errors

Found-by: gcc (Debian 11.3.0-3) 11.3.0
Change-Id: I2039cf66030030458bd247a31adc0621b9d033e6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-08 16:21:59 +00:00
Yu-Ping Wu 7f339c6050 mb/google/corsola: Correct EC-is-trusted logic
With Cr50, the GPIO EC_IN_RW_ODL is used to determine whether EC is
trusted. However, with Ti50 where corsola has been switched to, it is
determined by Ti50's boot mode. If the boot mode is TRUSTED_RO, the
VB2_CONTEXT_EC_TRUSTED flag will be set in check_boot_mode(). Therefore
in the Ti50 case get_ec_is_trusted() can just return 0.

The current code of get_ec_is_trusted() only checks the GPIO, which
causes the EC to be always considered "trusted". Therefore, correct the
return value to 0 for TPM_GOOGLE_TI50.

BUG=b:235053870
TEST=emerge-corsola coreboot
TEST=firmware-DevMode passed in kingler (with Ti50)
BRANCH=none

Change-Id: I59b16238bfb487832ef618668c0f9addc1ee7937
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64998
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08 14:58:17 +00:00
David Wu b95ebf9fcf mb/google/brask/var/kuldax: add fw_config and enable BT offload
add fw_config probe for auido and enable BT offload support.

BUG=b:232419816 b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08 12:53:19 +00:00
David Wu 7524c8dae5 mb/google/brask/var/kuldax: Update overridetree
Update override devicetree based on schematics.

BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08 12:53:01 +00:00
David Wu e77cd0ec71 mb/google/brask/var/kuldax: Update gpio table
Based on latest schematic to update the gpio table.

BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08 12:52:40 +00:00
Arec Kao 8e304fe40d mb/google/brya/var/redrix: Configure camera EEPROM power always on
Remove EEPROM power source interconnect with camera power on/off
and keep it always on.
There appears to be a rare case where the camera EEPROM is not
able to be read from. As a workaround, this patch leaves the
EEPROM power rail on in S0.

BUG=b:229049914
TEST=tested the changes with redrix 5MP(ov5675/hi556) camera.

Change-Id: I9efab9bb65632a73c1c2635729c38a2aa14c69b2
Signed-off-by: Arec Kao <arec.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-08 12:52:17 +00:00
Tim Wawrzynczak 5e1f33bf6a mb/google/brya: Add GPS _DSM subfunction support for Nvidia GPU
The _DSM subfunction for the Nvidia GN20 supports 1 additional
subfunction, known as GPS, which is required to support GPU Boost. This
implementation is minimal, essentially letting the GPU manage its own
temperature.

BUG=b:214581372
TEST=abuild

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08 12:51:33 +00:00
Tim Wawrzynczak 9803964301 mb/google/brya/var/agah: Fix ACPI power sequencing
Now that the power sequencing for the GPU is in a better shape, ensure
that the ACPI code that performs power sequencing matches the C code
that does the same.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08 12:50:48 +00:00
Tim Wawrzynczak 917ef5323c mb/google/brya/var/agah: Add delays to GPU power off sequence
During the GPU power down sequence, each power rail should reach below
at least 10% before the next rail is sequenced down; based on scope
shots for a board, conservative delays between each rail are added;
they will likely be more fine-tuned later on.

BUG=b:233959099
TEST=sequence verified by EE

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I28ada3a01b86996e9c7802f8bd18b9acda6bb343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08 12:50:31 +00:00
Zanxi Chen 097b9dd8e3 mb/google/corsola: Enable ps8640 for steelix
Currently, the display does not work in steelix. Steelix uses ps8640
eDP bridge IC, which is different from its reference board kingler.
So we should enable ps8640 for steelix.

BUG=b:232195941
TEST=firmware bootsplash is shown on eDP panel of steelix.

Change-Id: I8c6310794c89fc8aa0e69e114c1f7ebd5479c549
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-08 03:51:24 +00:00
Yu-Ping Wu ae1e702e7b drivers/tpm/cr50: Add TPM IRQ timeout Kconfig option
The current 10ms timeout for SPI TPM IRQ is not enough for platforms
using ti50 (such as corsola). Therefore, introduce a new Kconfig option
'GOOGLE_TPM_IRQ_TIMEOUT_MS'.

For platforms using cr50, we need to support legacy pre-ready-IRQ cr50
factory images during the initial boot, so the timeout remains 100ms for
I2C TPM and 10ms for SPI TPM. For all the other platforms using ti50,
the default timeout is increased to 750ms, as suggested by the ti50 team
(apronin@google.com).

BUG=b:232327704
TEST=emerge-corsola coreboot
BRANCH=none

Change-Id: I8dbb919e4a421a99a994913613a33738a49f5956
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-08 00:28:27 +00:00
Tyler Wang 20b58bc882 mb/google/nissa/var/craask: Add MIPI camera settings
Add OVTI8856 information for craask

BUG=b:232656913
TEST=Build and boot on craask

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ice490f31e9ab8fffff6a7a5d24f769efea91188d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-07 23:44:16 +00:00
Martin Roth 124c418ccf util/util_readme: update to give additional information
Add a note to the top of the util.md document saying not to edit it.

The Documentation/util.md file had been updated to contain additional
information at the bottom.  This copies that information into the file
after it's been created.

Change-Id: I4b08439420ceb706df62e3949406585ea34c1514
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 15:49:56 +00:00
Martin Roth 56846091f1 util, Documentation: Run util_readme.sh to regen util.md
Change-Id: Ie14204d0637bb5081e2fae4a9a0e2590bf7abeeb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 15:49:27 +00:00
Julius Werner 423cd06fa6 cbfstool: Expand CBFS verification validity check
This patch adds a new line to `cbfstool print -v` output that records
the overall CBFS verification health of the image. While this info was
already visible from individual fields before, it's nice to have a
one-stop location to see "this is a good image" without having to
carefully parse a lot of output manually.

Also add a few lines to the Makefile that check whether this field is
valid for the final image (it always should be, but hopefully this check
will allow us to catch regressions like the one fixed by CB:64547 sooner
in the future).

BUG=b:233263447

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1b74b01a55b22294556007aaee835d0fdb9e1c63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-07 12:57:25 +00:00
Bill XIE bb1e37e76b payloads/external: Reword help of SEAGRUB_ALLOW_SEABIOS_BOOTMENU
The sentence about "to bypass the secure mechanism implemented in
the GRUB runtime config" sounded confusing, so reword it.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I9c6f40d6d11d459fe4be40a624921c2632a89564
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-07 12:56:18 +00:00
Bill XIE 1003670da0 Docs: Reword and extend SeaBIOS description
The sentence about using SeaBIOS as secondary payload sounded
confusing, so reword it. While at it, improve and extend on SeaBIOS
features.

Change-Id: Ic06b9f56ab8082f2e6eff5fd8d31525429fd948d
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-07 12:56:01 +00:00
Shon d617980b0a mb/google/brya/var/vell: Add new LP5 RAM ID
Add the support LP5 RAM parts for vell:
DRAM Part Name                 ID to assign	Vendor
H58G56AK6BX069                 2 (0010)		Hynix

BUG=b:227595062
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: Ibe09285c15b28ceeb6ab0d6c94f90e00584ac07d
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-07 12:55:33 +00:00
Arthur Heymans bab9e2e6bd arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.

Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-07 12:54:39 +00:00
Kyösti Mälkki 11cac784ff Replace some ENV_ROMSTAGE with ENV_RAMINIT
With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.

Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 12:53:19 +00:00
Subrata Banik 0310d34c2f cpu/intel/microcode: Have provision to re-load microcode patch
This patch provides an option to reload the microcode patch a.k.a
second microcode patch if SoC selects the required
RELOAD_MICROCODE_PATCH config.

There is a new feature requirement starting with ADL to re-load the
microcode patch as per new Mcheck initialization flow.

BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS. Able to re-load
microcode patch as below:

[INFO ]  microcode: Re-load microcode patch
[INFO ]  microcode: updated to revision 0x41b date=2022-03-08

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a3c29b3c25fccd31280a2a5a8d4fb22a6cf53bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64833
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-07 12:52:00 +00:00
Subrata Banik bdea3524b0 soc/intel/cmn/mp_init: Create helper function to load microcode
This patch creates a helper function named `initialize_microcode()`
to load microcode and ease for all function to peform loading
microcode using this helper function.

BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7155fc2da7383629930ce147a90ac582782fa5ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-07 12:51:23 +00:00
Subrata Banik e43adb67bc soc/intel/cmn/block/cpu: Set BIOS_DONE on all CPUs
As per Intel Processor EDS, BIOS_DONE bit needs to be set on
all CPUs via MSR.

Also, implement a function to perform any SoC recommended CPU
programming prior to post CPUs init. At present calling
`cpu_soc_bios_done()` for all CPUs from `before_post_cpus_init()`.

Note: It is expected that `before_post_cpus_init()` will be
extended with other CPU programming recommendations in follow up
patches, for example: reload microcode patch etc.

BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8066cd724c9f15d259aeb23f3aa71a2d224d5340
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-07 12:51:00 +00:00
Subrata Banik 801dbf4f09 soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices
This patch implements heci_init() API that perform initialization of
all HECI devices as per MAX_HECI_DEVICES config.

BUG=none
TEST=Able to build and boot google/taeko with this change. No CSE
error observed with `heci_init()` called from romstage.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-07 12:50:29 +00:00
Bora Guvendik 6445023115 mb/intel/adlrvp: Add VBT for adlrvp with Raptor Lake silicon
Board id is same so use cpuid to decide to use ADL or RPL VBT.

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec

Change-Id: I954c228f82110c3e7c8474e47cabab8220ff19b9
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64672
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-07 12:49:41 +00:00
Bora Guvendik 6fbdedd1d2 mb/intel/adlrvp: Add initial code for adlrvp with raptorlake silicon
Take adlrvp_p as a baseline code and add a new variant of ADL RVP
with Raptor Lake silicon.

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I880abe0f300118f461523173cc0d50a2fbc99e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07 12:48:47 +00:00
Bora Guvendik 225e79b960 vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3172
The headers added are generated as per FSP v3172

In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I5aa0611b19bb4f6667a95d2539cc2d17de6dcf07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07 12:48:23 +00:00
Bora Guvendik 42d3cc719c vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3127_05_8
The headers added are generated as per FSP v3127_05_8.

In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=none

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9dd14468ec09bfe1a0904686e66d37a7389efdd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07 12:47:59 +00:00
Fred Reitberger 96f7b96866 soc/amd/common/block/cpu/: Make ucode update more generic
Use the equivalent cpuid in the microcode header to name the update file
in cbfs. This allows the SOC to directly locate its microcode file when
there are multiple processor revisions.

TEST: Loaded a chausie with sabrina, cezanne, and picasso microcode
files and booted. Verified that only the sabrina microcode file was
successfully loaded

Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-07 12:47:40 +00:00
Won Chung 749f5bd333 mb/google/guybrush: Add ACPI _PLD custom values
This patch uses ACPI _PLD macros to add custom values for USB ports.

   +----------------+
   |                |
   |     Screen     |
   |                |
   +----------------+
C0 |                | C1
A0 | MLB         DB | A1
   |                |
   +----------------+

BUG=b:232298307
TEST=None

Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ic9c45aebaf02a16b755f4731e1e3b46cd5dec829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07 12:46:32 +00:00
Won Chung b344b3c2c6 mb/google/skyrim: Add ACPI _PLD custom values
This patch uses ACPI _PLD macros to add custom values for USB ports.

   +----------------+
   |                |
   |     Screen     |
   |                |
   +----------------+
C0 |                | C1
A0 | MLB         DB |
   |                |
   +----------------+

BUG=b:232298017
TEST=None

Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Idca3dd468f1b9fde37a1bbf20d65768032c7160b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07 12:46:13 +00:00
Lean Sheng Tan f6f9b30691 mb/intel/ehlcrb: Store vboot VBNV in SPI flash
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I0d609f0db475877d0ef1f47ab89c34dccb6e16d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-07 12:45:30 +00:00
Lean Sheng Tan 88cd1a73e0 mb/intel/ehlcrb: Update vboot kconfig selections
Since many vboot settings are heavily tuned for Chrome OS support,
use these vboot kconfigs for the non Chrome OS use case and tune for EHL
CRB vboot support.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ie1ffd4973fb18bbca5c5b9c888a4dd0e662b1574
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-07 12:45:17 +00:00
Ian Feng 2c89d08a58 mb/google/skyrim/var/skyrim: Add audio codec and amp support
Add two combination:
1. ALC5682I-VS and ALC1019
2. NAU88L25 and MAX98360

BUG=b:227165780, b:228879074
TEST=emerge-skyrim coreboot chromeos-bootimage

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I36d7b5c4e88825ceaa6922d9e3bed366f55a0d81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 12:42:32 +00:00
Jon Murphy f658b35889 mb/google/guybrush: Remove TODO's and update text
Remove TODO's for dummy DXIO descriptors, update comment
to reflect what they are.  These devices are needed for the
platform to function properly.  Also remove the TODO for
DDI descriptors as they are functioning correctly.

BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1535c08cac3f0bcb30061aba2aa593eb22109387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 12:39:24 +00:00
Julius Werner 23d2465720 commonlib: Clean up compiler.h
This patch contains several minor cleanups related to compiler.h:

- Replace __always_unused() (which is a Linux-specific concept that
  doesn't make sense without also having __maybe_unused(), and had zero
  uses in the codebase) with __unused() which moves here from helpers.h

- Add __underscores__ to the names of all attributes in the compiler
  attribute shorthand macros. This is necessary to make them work in
  files where the same name was already used for an identifier (e.g.
  cbfstool/cbfs.h's `unused` array of file types).

- Remove libpayload's own copy of compiler.h and make it directly pull
  in the commonlib/bsd copy.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9644da594bb69133843c6b7f12ce50b2e45fd24b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-07 12:34:35 +00:00
Subrata Banik 6876f49b7e soc/intel/meteorlake: Refactor bootblock SoC programming code
This patch ensures the IP initialization being done as part of MTL
bootblock code is able to complete the bootblock phase without any
visible hang.

The re-ordering in the MTL bootblock SoC programming is required to
ensure the SA early initialization is taking place prior to
performing any PCI Read/Write operation (like P2SB bar enabling for
IOE die etc.).

Additionally, Fast SPI init takes place prior to enabling ROM caching
etc.

BUG=b:224325352
TEST= Able to build and start booting the MTL simics.
Without this change, the code execution is stuck as below:

[NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG]  IGD: device id ffff (rev ff) is Unknown
[INFO ]  PMC: Using default GPE route.
[INFO ]  VBNV: CMOS invalid, restoring from flash
[ERROR]  init_vbnv: failed to locate NVRAM
[EMERG]  Cannot locate primary CBFS

Able to detect the Flash and reading the SPI flash layout in proper
with this change as below:
[NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG]  IGD: device id ffff (rev ff) is Unknown
[INFO ]  PMC: Using default GPE route.
[INFO ]  VBNV: CMOS invalid, restoring from flash
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1804000.
[DEBUG]  FMAP: base = 0x0 size = 0x2000000 #areas = 33
[DEBUG]  FMAP: area RW_NVRAM found @ 112b000 (24576 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-06 17:52:32 +00:00
Subrata Banik ea4f8c28fd soc/intel/meteorlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.

Test=Boot MTL simics and check cbmem -c | grep 'CBFS: Found'
lists all stages.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5dc5d5b99003b59b2262bd1e4eb5ccb11d721195
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-06 17:52:03 +00:00
Ravi Sarawadi b8224f48fe soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
Base code is based of Intel Alder Lake SOC code.

List of changes:

1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
	vol1 #621483, vol2 #640858

TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-06 17:51:31 +00:00
Tim Wawrzynczak 3d79f7f13e mb/google/brya/acpi: Add support for NVPCF _DSM subfunction
The Nvidia GPU kernel driver supports another _DSM subfunction which
is known as NVPCF (Nvidia Platform and Control Framework). The
subfunction informs the kernel driver about Dynamic Boost parameters,
which is done at init time, but can also be changed dynamically.

BUG=b:214581372
TEST=build

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-06 16:18:43 +00:00
Arthur Heymans b97a303fa6 cpu/amd/agesa: Use common MRC_CACHE code to save S3 data
Use the common code to save data for fast boot or S3 resume.
An notable improvement that comes with this, is that the same 4K page
is not rewritten all the time. This prolongs the hardware's life.

TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.

Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44295
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-06-06 08:58:30 +00:00
Arthur Heymans 750d57ff5d drivers/amd/agesa: Don't save regular boot MTRR to flash
Save the regular boot MTRRs that are restored on the S3 path during
the CPU init in cbmem instead of storing them to the SPI flash.

This was probably done because historically this code run with late
cbmem init (in ramstage).

TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.

Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44294
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-06-06 08:57:09 +00:00
Arthur Heymans df3d97e821 drivers/amd/agesa/s3_mtrr.c: Save MSR for S3 using an array
The size of the data used is fixed in this function so there is no
need for this aritmetic.

The function signature will be changed in a followup commit.

The cache_disable call is dropped as all the codepaths calling the
restore_mtrr function do this already.

TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.

Change-Id: I3c6df8951d39695cddd4635360d6407d4d001b0a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44293
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-06-06 08:56:32 +00:00
Dtrain Hsu 0b917bde36 mb/google/brya/var/kinox: Set power limit based on charger type
Set different power limit values using host command to detect charger
type from ec.

Scenario:
1. With 90W customized adapter, set to baseline.
2. With 170W customized adapter, set to performance.
3. With above 90W barrel jack/type-c adapter, set to performance.
4. With below 90W barrel jack/type-c adapter, set to baseline.

BUG=b:231911918
TEST=Build and boot to Chrome OS

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9c8a5a7de8249e61468e277ec55348b660253c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-06 06:57:21 +00:00
Lean Sheng Tan 0cc82d6e41 mb/prodrive/atlas: Increase CBFS size to 8MB
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05 21:07:59 +00:00
Lean Sheng Tan 37a407fead MAINTAINERS: Add Maintainers for Intel Elkhart Lake SoC
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I165dc152af305b8df2d5e0c9396e11087004b3c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05 21:07:26 +00:00
Lean Sheng Tan a29452af47 MAINTAINERS: Add Maintainers for Prodrive Atlas Mainboard
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I5a8681a207149c11402aa51df1878746560c5b6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05 21:07:03 +00:00
Lean Sheng Tan cb14e86dd4 mb/prodrive/atlas: Add data.vbt for 4 DPs support
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05 20:02:33 +00:00
Matt DeVillier 08617e3f61 mb/google/octopus: Demote NHLT log messages from error to info
Change-Id: Ib2d0c6a23b66e6e61cc8ea09a443e19a4b37c66d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-05 20:00:10 +00:00