4 commits

Author	SHA1	Message	Date
Ronald G. Minnich	da7ee9fa07	These changes incorporate steve goodrich'es fixes, and one bug that is ... disabled. cs5536: add new entires for SB control etc. cs5536.c: chip_enabled function moved to chip_init, so it only gets run once. IRQ setup improved gx2def.h: new defines added vr.h: new file, with new def's for virtual register control. mainboard config.lb: new entries added for nb and sb control. chipsetinit.c: new controls added -- I forget all the details :-) grphinit.c: new function added northbridge.c: new IRQ control added. FlashChipSetup added, controlled by chip info setupflash struct member. Currently, if enabled, this hangs OLPC in linux PCI scan. chip.h: new struct members added for unwanted device enable, flash setup git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1	2006-07-21 19:21:38 +00:00
Ronald G. Minnich	fb93749642	changes from AMD for making OLPC video work. ... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1	2006-06-10 22:57:15 +00:00
Li-Ta Lo	d8d8fffa0e	minor modification ... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1	2006-04-13 17:00:38 +00:00
Ronald G. Minnich	4b8cf1d30a	added chipsetinit function, many defines. addec call to chipsetinit to ... northbridge.c builds fine on lippert git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1	2006-04-10 23:32:23 +00:00