Commit Graph

8483 Commits

Author SHA1 Message Date
Patrick Georgi e135ac5a7e Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic
  LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages

Future work:
- remove the compile time special case
  (requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
  not required anymore (eg. can SMM use the LAPIC timer?)

Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 23:51:52 +01:00
Stefan Reinauer bdc1816b23 Fix technexion tim5690 board VGA handler
When dropping ramstage.a, unused functions with unresolved
symbols are not silently dropped anymore. This makes the
tim5690 compilation fail.
This fix makes sure we don't compile in the int15 handler code
when we don't set CONFIG_VGA_ROM_RUN

Change-Id: If6872c983d9fd811eb33259421f94b551f3b9b34
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1929
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-27 22:19:22 +01:00
Dave Frodin 23023a5691 Enable the FCH GPP port prior to device enumeration
Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1873
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27 22:04:24 +01:00
Stefan Reinauer 8247583058 Drop duplicate files that prevent building without ramstage.a
When dropping ramstage.a duplicate symbols in ramstage
will start breaking the build. Hence drop all the duplicate
functions implemented by mainboards that have those functions
in generic or component code already.

Change-Id: I5cf8245c67b6f0f348388db54256d28f47017a61
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1865
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-27 22:03:37 +01:00
Patrick Georgi f33e395213 build system: Split linking into multiple steps
After collecting dependencies for ramstage, add an intermediate step
in which object files are linked per directory. The results are then
linked into the final binary.

This reduces the maximum command line length and might also help with
future use of LTO linking.

Also adapt the lint test for build dir handling, since printall
doesn't provide individual object files for ramstage anymore.

Change-Id: Ie40febd8c1eaf4609944eedeab46d870639e53df
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 22:02:02 +01:00
Patrick Georgi 79f9010e80 build system: Add hook to postprocess classes (object lists)
This will be used to minimize the ramstage class, to avoid command
line lengths to exceed the limit on mingw, esp. after we got rid
of ramstage.a

Change-Id: I80582d04476545c275e8d1d08fb52a99f58cebcc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 22:01:56 +01:00
Patrick Georgi 6999217ab6 build system: Eliminate special case for c_start
c_start.o has a special case in the build system, which we can
eliminate, somewhat simplifying the build.

To ensure that the entry point is at the beginning, introduce a
new section .textfirst that is placed appropriately. In principle
the ENTRY() definition in the linker script should be enough, but
better be safe.

Change-Id: I9737f7f5731e12ceb2119eb432b0e09832bc53fa
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1909
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27 22:01:02 +01:00
Patrick Georgi 23f38cd05c Get rid of drivers class
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.

These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.

With ramstage.a gone, we can drop this special class, too.

Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27 22:00:49 +01:00
Patrick Georgi 18607f717e Drop ramstage.a
ramstage.a has two issues:
1. duplicate source filenames don't survive the ar(1)
   treatment properly (so files aren't considered)
2. ld doesn't resolve symbols if it isn't forced to, in
   particular no overrides of weak symbols

Downside: The resulting binaries get slightly larger.
Link time optimizations should fix that, as would tighter
rules in the build system (to not compile unused code in
the first place).

Change-Id: Iaae771ec8f92b42069237acd3b79c14e5bf9c03d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1566
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27 21:59:26 +01:00
Patrick Georgi b6f765e7c8 Provide weak empty declarations of all chip_ops used on a board
sconfig creates empty defaults for all chip_ops, which can be overridden
by drivers simply by providing a concrete implementation.

Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1567
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 21:48:22 +01:00
Patrick Georgi 28b900afbd libpayload: Add _ and + to USB HID keymap
Slightly more complete keymap

Change-Id: I4fef6b8f75ab07cb20a3a8ccd7eaad81c9fe719f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1922
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 18:29:31 +01:00
Nico Huber e3abd3bfbb roda/rk886ex: Correct COMB irq reading / reduce warnings
The calculation of COMB's irq reading was wrong by the 4-bit shift.
Also, the asl compiler warned about the splitting in lo/hi bytes which
seems unnecessary.

Change-Id: Ia5101d5a19f68c2da827d7e37a18922f959604c7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1923
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 18:29:20 +01:00
Patrick Georgi f5e0fd888d roda/rk9: Fix for VGABIOS changes
Forgot to update the rk9 for the unified VGABIOS handling.

This applies to rk9 what is done for other boards in commits
	3c84261e84
	d5d340695b

Change-Id: I892b7d81927e277778c1c5251d27416fa79c9868
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1924
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 18:27:43 +01:00
Zheng Bao b8117b0622 SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
For SST chips, the Write-Status-Register instruction must be
executed immediately after the execution of the
Enable-Write-Status-Register instruction, instead of Write-Enable.

Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1919
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 11:03:52 +01:00
Patrick Georgi 1a5301dd33 abuild: only rebuild boards if requested or after a broken build
That used to be the behaviour, and it's quite useful to incrementally
fix bugs across the tree.

Change-Id: I3e30cbdcf01631bc29f892054caa3babb0969beb
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1888
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 10:07:54 +01:00
Zheng Bao 536b53ea6d xcompile: Add missing XGCCPATH
XGCCPATH is missing in new xcompile.

Change-Id: I177f54189be445404a4a61419064d3c414b8a30c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1921
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 09:22:10 +01:00
Patrick Georgi 021b7033fb roda/rk9: New mainboard
Roda RK9 is a notebook based on the GM45/ICH9 platform using DDR3 memory.
http://roda-computer.com/products/notebooks/rk9/

Tested with various Linux versions, known to work:
- 2x4GB RAM
- IGD
- HD Audio
- UHCI, EHCI
- AHCI
- NIC
- PCI
- PS/2 keyboard
- serial console
- ACPI lid switch
- ACPI battery/AC events
- power off, reboot

Change-Id: I7299dccbff2eea3544363fdd4f49f05aa3dae7bc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1691
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 09:17:05 +01:00
Patrick Georgi e72a8a3047 intel/i82801ix: new southbridge, ICH9
Add support for ICH9 southbridge

Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 09:16:58 +01:00
Patrick Georgi 2efc8808b8 intel/gm45: new northbridge
The code supports DDR3 boards only. RAM init for DDR2 is sufficiently
different that it requires separate code, and we have no boards to
test that.

Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 09:16:18 +01:00
Nico Huber acd7d95251 Add initialization hook for chips
Add an init() function to the chip_operations which will be called
before bus enumeration. This allows to disable unused devices before
they get enumerated.

Change-Id: I63dd9cbfc7b5995ccafb7bf7a81dc71fc67906a0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1623
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 09:16:03 +01:00
Ronald G. Minnich e820e5cb3a Make xcompile support multiple architectures
With this change the the xcompile script now creates environment variables
for more than one architecture.

Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Change-Id: I349a1fd1d865ef16979f1dfd6aeca12b1ee2eed6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1915
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-11-27 02:06:07 +01:00
David Hendricks 534c8a013f Conditionally #include mc1468181rtc if CMOS_POST is enabled
This will omit the mc1468181rtc header if it is not needed. Currently
it contains a lot of inlined functions which depend on architecture-
specific IO.

Change-Id: I4ef1bc1362c159e0c780c3eade01af04f029f949
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1916
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-27 02:03:27 +01:00
David Hendricks 6b908d08ab Make POST codes written to IO port optional
This adds more configurability to POST codes. The current assumption
is that POST codes should be written to an IO port (e.g. LPC) if POST
codes are enabled. This changes the assumption so that POST codes can
be written to the serial console without being written to an IO port.

This enables POST codes by default using "default y" to avoid
changing current behavior.

Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1685
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 02:03:03 +01:00
Patrick Georgi d5d340695b Remove duplicate VGA BIOS interrupt handlers
Some boards have two instances of the int15 handler that supports
the onboard VGA BIOS, for YABEL and realmode.
These are now similar enough that they can be deduplicated.

Due to minor differences this requires manual effort.

Change-Id: I03ae314cb90dd65d96591ce448504aa961cbeb88
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1893
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:12:56 +01:00
Patrick Georgi 3c84261e84 yabel: Use X86_* instead of the more verbose M.x86.REG_*
Makes it more similar to what realmode looks like.

Change-Id: I4407431f2d979c43dd186114d67ed11845907afe
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1892
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:12:16 +01:00
Patrick Georgi 199b09cb7a x86 realmode: Use x86emu register file + defines
By using the (global) register file as defined by x86emu,
we can use the same register access for YABEL and realmode
interrupt handlers.

- the x86 realmode interrupt handlers changed in signature
- to access registers, use X86_$REGNAME now (eg. X86_EAX)
- x86_exception_handler still uses struct eregs *regs to
  avoid spilling the x86emu register file stuff everywhere

Coccinelle script that handled most of this commit:
  @ inthandler @
  identifier FUNC, regs;
  @@
  int FUNC(
  -struct eregs *regs
  +void
   )
  { ... }

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->eax
  +X86_EAX

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->ebx
  +X86_EBX

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->ecx
  +X86_ECX

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->edx
  +X86_EDX

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->esi
  +X86_ESI

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->edi
  +X86_EDI

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->eflags
  +X86_EFLAGS

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->vector
  +M.x86.intno

Change-Id: I60cc2c36646fe4b7f97457b1e297e3df086daa36
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:11:46 +01:00
Patrick Georgi 503af721a1 x86 realmode: Adapt to x86emu/YABEL style return codes
realmode int handlers must return the same codes as the YABEL
int handlers now: 1 for "interrupt handled", 0 for "not handled"
(ie. error).

Change-Id: Idc01cf64e2c97150fc4643671a0bc4cca2ae6668
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1890
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:06:24 +01:00
Patrick Georgi 3e77eb6d1e x86emu: Move realmode handler into own directory
It's really a feature in parallel to YABEL/x86emu. Reflect this in
the directory structure.

Change-Id: Ie88e4fa6bfef13d23c55b2db3faacbd90f8cc30b
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:05:00 +01:00
Idwer Vollering 6b11c8be45 crossgcc: update to acpica-20121114
Update acpica to release 20121114 and
update patches/ to build with this version of acpica.
Correct the creation of crossgcc-build.log
Bump CROSSGCC_VERSION.

Change-Id: I269454ebc3c78b5852e4a67e55bb5642edad191d
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1861
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24 08:54:53 +01:00
Nico Huber 0c2364c17c libpayload: Fix interrupt-queue cleanup for OHCI
We have to free TDs more carefully if they have been processed by the
controller yet. The current code tries to force the controller to post
them back to the done queue, but that seems wrong. We can't be sure,
when they get written back. This resulted in leaking TDs with an invalid
reference to a freed interrupt queue.

The new approach: Mark the interrupt queue to be destroyed and handle
the freeing later, when the controller posted the last TD to the done
queue.

Change-Id: I79d80a9dc89e1ca79dc125c4bbccbf23664227b3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1905
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24 08:54:04 +01:00
Nico Huber b9917c2068 libpayload: Rework connection state detection for OHCI
The connection state detection in the OHCI root hub driver was broken if
you used more than one device per root hub.

Change-Id: Ica5c735426beac45ef6f591ce68a72d8283a00f5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1904
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24 08:46:34 +01:00
Nico Huber be58fee28e libpayload: Handle errors in UHCI interrupt queues
If somethings goes wrong during an interrupt transfer, drop the
transfer.

Change-Id: I450c08a7a0bf23fbee74237e0355d4a726ace114
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1901
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-24 08:44:01 +01:00
Nico Huber 8c4d2f36a3 libpayload: Handle underruns in UHCI interrupt queues
If usb_poll() isn't called fast enough, the UHCI controller marks an
underrun interrupt queue as done (terminating the queue at the head).
We can recover from this situation, when usb_poll() gets called again,
and the queue is processed.

Change-Id: Id56c9df44d6dbd53cd30ad89dfb5bf5977799829
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1898
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24 08:43:49 +01:00
Nico Huber ce407e470d libpayload: Implement correct interrupt-queue linking for UHCI
The linking of interrupt queues into UHCI controller's framelist (in
uhci_create_intr_queue()) was incomplete. The implementation of
uhci_destroy_intr_queue() was even worse, looking like it wanted to
clean up more than uhci_create_intr_queue() did.

This patch follows the simple approach that we used for OHCI and EHCI:
Each slot in the framelist holds only one interrupt queue. Therefore, we
have to look for free slots each time we want to link an interrupt queue
into the framelist. In return, we have a much simpler structured
framelist.

With this, USB devices using interrupt transfers (e.g. keyboards) can be
detached cleanly from UHCI controllers. Also, more than one of such
devices can be attached without further risk.

Change-Id: I07b81a3b6f2cb3ff69515c973b3ae6321ad969aa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1897
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24 08:43:21 +01:00
Nico Huber cd587f110b libpayload: Make USB HID support multiple keyboards
The USB HID driver had some static variables with keyboard state. This
moves them to the driver's instance, so multiple attached keyboards
don't effect each other.

Change-Id: I3f1ccfdea95062b443cebe510abf2f72fdeb1916
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1907
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-23 18:19:06 +01:00
Nico Huber af169f4dd5 libpayload: ehci: Prevent some race conditions
Prevent race conditions, when an interrupt-queue underrun occurred and
the controller is currently working on our queue head or a transfer is
still in progress.

Change-Id: Ia14f80a08071306ee5d1349780be081bfacb206a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1902
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-23 18:18:59 +01:00
Nico Huber b2db28babe libpayload: Detach devices behind removed USB hubs
When a USB hub got removed, we should also remove all devices that
were attached to it.

Change-Id: I73c0da1b7570f1af9726925ca222781b3d752557
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1903
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-23 18:18:31 +01:00
Nico Huber ef88e102bb libpayload: More compliant error recovery in USB MSC
If an endpoint gets stalled by an MSC device, after successful
transmission of a command (CBW), we should still ask for the status
(CSW). Otherwise, the driver and the device get desynchronized on the
command tags.

Change-Id: I53167f22c43b3a237cb4539b3affe37799378b93
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1900
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-23 18:18:14 +01:00
Nico Huber 86c686a76e libpayload: Reduce error output from EHCI
Stalled transfers are not fatal, so don't spew on the console on every
tiny failure.

Change-Id: I175c1e83a6af09c1abbd43d045ed6dbf0c79f871
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1899
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-23 18:18:02 +01:00
Nico Huber e8a71d34cd libpayload: Fix random warnings
dump_td() is orphaned but looks useful => commented out.

The delay identifier shadowed the global one => renamed to total_delay.

Change-Id: I4f3766a07db9194b2552ebf9302bd7ef8a66371f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1895
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-23 18:17:37 +01:00
Nico Huber 4f83d1b0c6 libpayload: ehci: Fix warnings about discarded volatile
We can trust free() and memset() to work correctly on volatile
references, so cast volatile pointers to (void *) when calling them.

Change-Id: Ieff7f78133b72f303349cca0a0ca3bbf37ec52bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1896
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-23 18:17:31 +01:00
Nico Huber ba22e4c3fd libpayload: Fix some missing-prototype warnings
usb_controller_initialize() is not declared in any header file nor
called from outside of usbinit.c, so make it static.

set_configuration() looks like beeing non-static on purpose (like the
other helpers around it in usb.c), so put a prototype into usb.h.

Change-Id: I08d93b3769d8398bb43462d9afdfeec81fef93ec
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1894
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-23 18:17:24 +01:00
Nico Huber 7a32e88f12 libpayload: Fix memalign() for fragmented alignment regions
Found a bug in the memory allocator ;-)

If the total free space in an alignment region is large enough for an
allocation but fragmented, such that there is no contiguous, sufficient
large, free space in the region, memalign() was looking at the same
region again and again in an endless loop. The advancing to the next
region was just missing.

Change-Id: I3fad833804675ee495577ca2749b007f46b5ff69
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1906
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-11-23 18:17:08 +01:00
Patrick Georgi 0a3f2393ae crossgcc: properly test for flex
This is no GNU tool, so testing for "GNU" in the version string
is bound to fail.
We now accept everything that returns success on "flex --version"
and then hope for the best.

I tested both cases

Change-Id: If325f613fde1648847b998b7e8e5782d0f22b484
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1884
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-22 08:08:48 +01:00
Dave Frodin 73be43a139 Persimmon: Disable the unused GPP PCIe clocks
Change-Id: I4128af7912bec090bbd48acc1b20d0452e7a4a28
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-20 23:59:54 +01:00
Stefan Reinauer 8ada1526df Unify use of bool config variables
e.g.
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS

This will make it easier to switch over to use the config_enabled()
macro later on.

Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-20 21:56:05 +01:00
Stefan Reinauer 82ecf4c582 secondary.S: Fix dropping ramstage.a
This unused code was not silently dropped as before.

Change-Id: Ic76c58e233869a60c3a8a27c2efc2182b3a4442d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1863
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-20 01:52:53 +01:00
Stefan Reinauer 40f36e0d8d Make sure only one udelay function is available
The Agesa wrapper and UDELAY_TIMER2 define their own timer functions,
so don't shove in UDELAY_IO

Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1864
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-20 01:52:20 +01:00
Patrick Georgi 0d8267464d siemens/sitemp_g1p1: Drop copy of cmos checksum calculation
This code used a special case for checksum calculation to
prevent the century byte from messing things up, since
writes "sometimes" didn't happen.

That should be stable now, so the special case isn't necessary.
Downside: On century rollovers (ie. 1999-12-31, 2099-12-31)
CMOS will be reset to the defaults.

Change-Id: Ibe589a1ec953b7b3ba39be30cebd9fc2b27326ae
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1870
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-19 22:06:55 +01:00
Patrick Georgi d8e6d4085f bootblock: Guard CMOS rewrite in disable/enable RTC
This ensures that there's only one disable/enable cycle for
the entire rewrite instead for every single byte.

Change-Id: Ic06e6dcb08976d158ff784660838c0fbad875176
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1869
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-19 22:06:51 +01:00