Commit Graph

13214 Commits

Author SHA1 Message Date
huang lin d5fb66e060 rk3288: add gpio
BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I63b4a62f624d34f7028321cb4576cbdb9cd10817
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3606d7eb06d66e23f4ee7ecb6862d23bde3acfd2
Original-Change-Id: I3e0cff1c6de464a8a79e30e239cfb0960cbae253
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209460
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8864
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-03-24 15:25:18 +01:00
huang lin 441a57894a rk3288: add i2c
BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I23af280764eb28d3f6b215ab32553fe42ee73272
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: abf5c14c8b32573107d2a1c73a752e740264db7e
Original-Change-Id: I46257cc71cc3cd1e867edf589ddf09f7990d6784
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209462
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8863
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-03-24 15:25:10 +01:00
huang lin 817e455d38 add make_idb.py & update bootblock
BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: Ica7b2bf2cf649c2731933ce59a263692bb2c0282
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ba9c36daedc749748f45e68a84f8c34c636adb1c
Original-Change-Id: Ia0e4e39d4391674f25e630b40913eb99ff3f75c4
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209427
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8862
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-24 15:24:52 +01:00
huang lin 7333e1fbc3 rk3288: add media
BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I74b30ecfe40c039855b835db0dfd0cd25adf960e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a30378a3152c930029a5b170cc6bf46180b5c7b8
Original-Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209468
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8860
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-03-24 15:24:49 +01:00
huang lin 5a9b8f6aea rk3288: add iomux operation
BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: Ia19f8084a945992d9f252eb080c6c5c9990ac7de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30d02610e8e1e018025c2c1c970fb5b33d67d51b
Original-Change-Id: I8f273f8850e4792ca976bb7c2ed39cbe501401f2
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209461
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8861
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-03-24 15:24:31 +01:00
huang lin 630c86d8cc rk3288: add spi
BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I858ac723d640dde8538aebb968fcff364fa7207c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8253a9dbad2afdf9eb9a8554fd355e6815887407
Original-Change-Id: Ib6ee7e3092429a3e47b102751ed6a88aeb9ee7d3
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209429
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8859
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-03-24 15:24:27 +01:00
jinkun.hong 503d12191d rk3288: add clock module
Call rkclk_init() in bootblock stage.
apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz
arm clk = 816MHz, DDR clk = 300MHz, mpclk = 204MHz, m0clk = 408MHz
l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz
aclk = 148.5MHz, hclk = 148.5MHz, pclk = 74.25MHz

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: Id5967712e25df5be3a90f5d9ebe8671034deff68
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d35d9fe7b5925291e9303e5eb21d20dbbdee99d9
Original-Change-Id: I97d953258039f6caa499cef4462be8f1a05ce2ab
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209428
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-03-24 15:24:19 +01:00
Duncan Laurie 338c617cc5 vboot: Add support for OPROM_MATTERS and SLOW_EC
In order to display a "update in progress" screen on devices with
a slow EC or PD chip it may be necessary to also load the VGA
Option ROM when doing EC software sync.

This adds config options for VBOOT_EC_SLOW_UPDATE which simply sets
a flag in the input parameters that is already handled by vboot.

It also adds a config option for VBOOT_OPROM_MATTERS which is a bit
more tricky in that it sets a flag in input parameters, but also
needs to keep track of the option rom being loaded and pass that
flag into VbInit as well.

Since VbInit will clear the NV bit for option rom loaded the check
that is done in vboot_wants_oprom() needs to first compare against
the vboot handoff copy of the input flags.

BUG=chrome-os-partner:32379
BRANCH=samus
TEST=manual testing:
1) in normal mode, with EC/PD in RW, ensure that they are rebooted
to RO and the VGA Option ROM is loaded and the wait screen is
displayed, and then the system is rebooted at the end and the
VGA Option ROM is not loaded.
2) same as #1 with EC/PD in RO already, same result
3) same as #1 with system in developer mode, same result except
there is no reboot at the end of software sync
4) same as #1 with system in developer mode and EC/PD in RO,
ensure that there is no extra reboot at the beginning or end of
software sync.

Original-Change-Id: Ic2b34bf9e7c6cc5498413fa1b8dff6e6207c9d0a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223831
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 7d7aa89238efb5081885f9386c8e872fc96f573f)

Change-Id: Ib7fb24e6e80e1f7e836bc62246ab9b3e056fd73d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-24 15:20:30 +01:00
Daisuke Nojiri 477dd18524 vboot: add vbnv_flash as template
this adds a flash vbnv driver for vboot to store non-volatile data in a flash
storage.

BUG=chrome-os-partner:32774
BRANCH=none
TEST=Built samus, veyron pinky, and cosmos
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: If5fc1b779722528134ad283fa030f150b3bab55f
Original-Reviewed-on: https://chromium-review.googlesource.com/222258
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 1916da67123680d379d8926380d797cf466b7994)

Change-Id: If5ff3542cc14139ec0b02cf5661c42a1b02da23e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24 15:20:09 +01:00
Daisuke Nojiri 97ea9c0516 vboot2: factory-initialize kernel space in tpm
this change makes coreboot initialize kernel space and backup space in the tpm
when no firmware space is found in the tpm.

BUG=chrome-os-partner:32410
TEST=Forced factory initialization and verified it went through without errors.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: I777e3cb7004870c769163827543c83665d3732b9
Original-Reviewed-on: https://chromium-review.googlesource.com/220412
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit d8c0c407bf0fed60d76441ada7bedd36f6fc3a38)

Change-Id: Icc3779125262b4499e47781991ebbf584abf074a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24 15:19:54 +01:00
Daisuke Nojiri 6abe7c6996 vboot2: avoid fall through when hard_reset is not implemented
this change makes prevent execution from falling through to unverified
code when hard_reset is not implemented. it also includes a few touch-ups.

BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None

Original-Change-Id: I9b02ab766172a62c98b434c29f310bc4a44f342d
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219625
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit d1f5207d83d2247b55f2bb9d02ac843305fc3ded)

Change-Id: I99dd5a2ca3a5369accb14408ea9d266bf60e7132
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24 15:19:36 +01:00
Daisuke Nojiri 35890170b5 vboot2: load decompressed stage directly to load address
this change allows vboot_load_stage to load a decompressed stage directly to the
load address without using the cbfs cache.

BUG=None
TEST=Booted Nyan Blaze.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: I76530276ff9a87b44f98a33f2c34bd5b2de6888f
Original-Reviewed-on: https://chromium-review.googlesource.com/219028
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 0ad6f7fee9df31e1b35d4df9a8c373516416a235)

Change-Id: I7abdbdda0cc549894dfb9d599a576bba0a4fadfc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8883
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-24 15:19:21 +01:00
Daisuke Nojiri 1bbac3fd24 vboot2: Make struct vb2_working_data cpu architecture agnostic
this allows vb2_working_data to be accessed from stages running on different cpu
architectures.

BUG=none
TEST=Built firmware for Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: Ife2844637af8bf9e0d032a50fb516d98b8f80497
Original-Reviewed-on: https://chromium-review.googlesource.com/217835
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 2b36749bc5a761003f00b7a0d17edb1629245b88)

Change-Id: Idc10f23ed2927717f5308f0112aa8113a683010e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8882
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24 14:48:22 +01:00
Daisuke Nojiri efddcfbb52 vboot2: separate verstage from bootblock
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over
the bootblock, then exits to the romstage. this is necessary for some SOC
(e.g. tegra124) which runs the bootblock on a different architecture.

With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock.
Then, the bootblock loads the romstage over the verstage and exits to the
romstage. this is probably necessary for some SOC (e.g. rockchip) which does not
have SRAM big enough to fit the verstage and the romstage at the same time.

BUG=none
TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544
Original-Reviewed-on: https://chromium-review.googlesource.com/212365
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Note: This purposefully is probably broken in vendorcode/google/chromeos
as I'm just trying to set a base for dropping more patches in. The vboot
paths will have to change from how they are currently constructed.

(cherry picked from commit 4fa17395113d86445660091413ecb005485f8014)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9
Reviewed-on: http://review.coreboot.org/8881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24 14:48:04 +01:00
Daisuke Nojiri 1b05d887d7 nyans: reduce code duplication in bootblock and romstages
this change reduces the code duplication of the bootblock and the romstages for
Nyans.

BUG=none
TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri)
Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a
Original-Reviewed-on: https://chromium-review.googlesource.com/214050
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>

(cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef
Reviewed-on: http://review.coreboot.org/8880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24 14:47:47 +01:00
David Hendricks dad16b1c58 vboot: Introduce kconfig variable for VBNV backing storage
This introduces a new kconfig variable to select the VBNV backing
store explicitly instead of inferring it from CPU/SoC architecture.

x86 platforms have historically relied only on CMOS to store VBNV
variables, while ARM-based platforms have traditionally relied on
the EC. Neither of those solutions are going to scale well into
the future if/when CMOS disappears and we make ARM-based systems
without an EC.

BUG=chrome-os-partner:29546
BRANCH=none
TEST=compiled for nyan_blaze and samus

Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I4a8dadfb6bb666baf1ed4bec98b29c145dc4a1e7
Original-Reviewed-on: https://chromium-review.googlesource.com/213877
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit d088fc71b2e2b45e826d3dedb8e536ad58b8d296)

Change-Id: Iea325a8c4d07055143e993d89b827f86b8312330
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8777
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23 20:22:08 +01:00
Furquan Shaikh 8c7c05a389 vboot: Update VBOOT_CFLAGS to include rmodules ccopts
rmodules ccopts contain information about specific arch like armv4,v7. Hence, it
is important to include them in VBOOT_CFLAGS

BUG=None
BRANCH=None
TEST=Compiles correctly for armv4 in rush

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id:
Original-Change-Id: I8f5509f753e28046678c3782d6f0b6210559f798
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209979
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit ca9f2f86ff1bc445abf5f97f61c04b6eccbd3e25)

Change-Id: I6cd7c47f33cf897d8ee96e7154222b3bfbe5221f
Reviewed-on: http://review.coreboot.org/8775
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23 19:53:46 +01:00
Daisuke Nojiri 79cac09cd1 vboot2: translate shared data to hand off to depthcharge
TEST=Built Blaze with USE=+/-vboot2. Ran faft: CorruptBothFwAB,
CorruptBothFWSigAB, CorruptFwBodyA/B, CoccurptFwSigA/B, DevBootUSB, DevMode,
TryFwB, UserRequestRecovery, SelfSignedBoot, RollbackFirmware.
BUG=None
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: I45a1efd4d55fde37cc67fc02642fed0bc9366469
Original-Reviewed-on: https://chromium-review.googlesource.com/205236
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 0a9e7f099251c33ce286fa8d704a3e021eac4d3e)

Change-Id: I5f61c03c66ca83a5837c14378905ba178aba5300
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8655
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23 19:53:09 +01:00
Aaron Durbin 302ed00cb6 chromeos: rename for easier patch merging
In order to more cleanly apply upcoming changes some files
will need to do a dance.

Change-Id: Ib50670743c10221785447490190ecdbff8c764fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8654
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-23 19:51:50 +01:00
Daisuke Nojiri 5799097be5 vboot2: read secdata and nvdata
This code ports antirollback module and tpm library from platform/vboot_reference.
names are modified to conform to coreboot's style.

The rollback_index module is split in a bottom half and top half. The top half
contains generic code which hides the underlying storage implementation.
The bottom half implements the storage abstraction.
With this change, the bottom half is moved to coreboot, while the top half stays
in vboot_reference.

TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link.
BUG=none
Branch=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e
Original-Reviewed-on: https://chromium-review.googlesource.com/206065
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-by: Luigi Semenzato <semenzato@chromium.org>

(cherry picked from commit 6b66140ac979a991237bf1fe25e0a55244a406d0)

Change-Id: Ia3b8f27d6b1c2055e898ce716c4a93782792599c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8615
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-23 19:51:47 +01:00
Sourabh Banerjee e73335ce8e libpayload: usb: xhci: set ENT flag in last Normal TRB
If a TD is comprised of one or more Normal TRBs and terminated with an
Event Data TRB, then the transition to the Idle state (and associated
Stream state save) could occur after all the data for the TD has been
moved (e.g. after Transfer Event TRBs have been executed), but before the
Event Data TRB is executed. Under these conditions, the execution of the
Event Data TRB is necessary to complete the TD, otherwise it does not
occur until the next time the Stream is scheduled. This could lead to the
lock up.

The Evaluate Next TRB(ENT) flag provides a means of forcing the execution
of a terminating Event Data TRB. Setting ENT flag in last Normal TRB makes
the xHC to evaluate the Even Data TRB.

BUG=chrome-os-partner:29375
TEST=Verified kernel boot-up on storm from previously failing USB stick.
     USB stick model: Sandisk Ultra USB 3.0 Pen Drive 32 GB
		      Strontium Jet USB 3.0 Pen Drive 32 GB

Change-Id: I092e2109c55c2274239c493cb67b47d730304ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7eefb3b2858c841165ae839d349d2a0be50fbcc8
Original-Change-Id: I4e123577ec5a5996d87d2fc52cb6cf5c571c9fae
Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220123
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8736
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23 18:41:18 +01:00
Jim Lin 654cf9c2d8 libpayload: EHCI: Support root-hub TT feature
If EHCI controller has TT (Transaction Translator) support in
root-hub, then we need to keep control over this controller when
USB keyboard (low-speed device) is connected to root-hub port.

Need to add "CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y" to config file
(e.g. payloads/libpayload/configs/config.nyan_big) to support this
feature.

BUG=chrome-os-partner:32355
TEST=Tested on nyan_big platform.
Press ESC+REFRESH+POWER keys on internal keyboard to power up.
Press Left Arrow or Right Arrow on USB keyboard to switch between
"English" and "Default Locale" in coreboot UI. Or unplug and plug
in device and try again.
Root hub <- low-speed USB keyboard
Root hub <- full-speed hub <- low-speed USB keyboard
Root hub <- high-speed hub <- low-speed USB keyboard

Change-Id: Iaa2823f64c8769fc808ee7a316c378f18f004e63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4ad57fd673d6dc8814fe99a4ac420566bb17e77b
Original-Change-Id: Id86a289bc587653b85227c1d50f7a4f476f37983
Original-Signed-off-by: Jim Lin <jilin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220125
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 17:57:40 +01:00
Vadim Bendebury 052b7fec07 Enable publishing of board ID where supported
These boards are supposed to be able to determine the board ID at run
time based on GPIO settings.

BUG=chrome-os-partner:30489
TEST=verified that all boards build. Checked that storm proto0 reports
     board ID of 0 on the console

Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210119
(cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733
Reviewed-on: http://review.coreboot.org/8722
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23 17:20:24 +01:00
Vadim Bendebury 81678809d5 storm: Add board ID calculation function
storm uses three GPIOs in tertiary mode, such that proto0 returns
value of 8 when the GPIOs are interpreted as a single tertiary number.

Adjust the calculated value to return board ID of 0 on proto0, and
monotonously incrementing values on newer boards.

BUG=chrome-os-partner:30489
TEST=when enabled, the board ID value of zero is reported on the console.

Original-Change-Id: I2ff8fd5cbc8d568877b6f8bf220e146893f1e4be
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210118
(cherry picked from commit 6ba24f31583933f02be111c8767ae9df56537011)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I35ee218df35a0924d4bb8fcbc6c875450a609f24
Reviewed-on: http://review.coreboot.org/8721
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23 17:20:21 +01:00
Vadim Bendebury 5e1a2d3fca Include board ID calculations only when necessary
For the majority of Chrome OS boards there is no need to include board
ID calculation in any stage but ramstage, where the ID should be
available for inclusion into the coreboot table.

BUG=chrome-os-partner:30489
TEST=build only, no other tests yet

Change-Id: I1451d52382bc48cc126d40267e0f61712f4a6d4b
Original-Change-Id: Ib9c06698a399d31e79a9b14143343ba2ad46d0fb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210117
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 27dd40e85bfcd0a38f388bad4d79f5fbb77a7566)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8720
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23 17:20:18 +01:00
Vadim Bendebury b0c302fd79 Publish the board ID value in coreboot table, when configured
Board ID value is usually of interest to bootloaders. Instead of
duplicating the board ID discovery code in different bootloaders let's
determine it in coreboot and publish it through coreboot table, when
configured.

BUG=chrome-os-partner:30489
TEST=none yet

Change-Id: Ia1e36b907ac15b0aafce0711f827cb83622e27bb
Original-Change-Id: Iee247c44a1c91dbcedcc9058e8742c75ff951f43
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210116
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit b2057a02db9391e2085b138eea843e6bb09d3ea2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8719
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23 17:20:13 +01:00
Vadim Bendebury d36ef6a51d ipq806x: implement GPIO API
Add implementation of the GPIO API defined in src/include/gpiolib.h.
Also, clean up the GPIO driver, make it use pointers instead of
integers for register address.

This requires a touch in the SPI driver, where the CS GPIO is toggled
and in the board function where it enables USB interface.

BUG=chrome-os-partner:30489
TEST=tested with the following patches, observed proto0 properly read
     the board ID.

Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210115
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2
Reviewed-on: http://review.coreboot.org/8718
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23 17:20:07 +01:00
Vadim Bendebury 9c9c336464 Generalize revision number calculation function
Some platforms use tertiary interpretation of GPIO input state to
increase number of distinct values represented by a limited number of
GPIOs. The three states are

- external pull down (interpreted as 0)
- external pull up (1)
- not connected (2)

This has been required by Nvidia devices so far, but Exynos and
Ipq8086 platforms need this too.

This patch moves the function reading the tertiary state into the
library and exposes the necessary GPIO API functions in a new include
file. The functions are still supposed to be provided by platform
specific modules.

The function interpreting the GPIO states has been modified to allow
to interpret the state either as a true tertiary number or as a set
two bit fields.

Since linker garbage collection is not happening when building x86
targets, a new configuration option is being added to include the new
module only when needed.

BUG=chrome-os-partner:30489
TEST=verified that nyan_big still reports proper revision ID.

Change-Id: Ib55122c359629b58288c1022da83e6c63dc2264d
Original-Change-Id: I243c9f43c82bd4a41de2154bbdbd07df0a241046
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209673
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c79ef1c545d073eaad69e6c8c629f9656b8c2f3e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8717
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23 17:20:04 +01:00
Vadim Bendebury fddf75e4af build: mips: add default compilation options
MIPS targets should be compiled with no position independent code
allowed, as the generated image often does not support short range
components reference.

BUG=chrome-os-partner:31438
TEST=with the rest of the patches included MIPS board urara builds
     successfully

Change-Id: I8ac2a2f6979d3b468159c9e29d07e022f48ab18a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e932b203db3e7cb510a7bf862d4538d55b6c7271
Original-Change-Id: I637dd44eb565447c18b2c3cdb022d0933c52fd20
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215677
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8822
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 15:35:12 +01:00
Paul Burton 6ea3eff6b7 console: Allow bootblock console on MIPS
In addition to ARM based systems, allow MIPS based systems to select
bootblock console support.

BUG=chrome-os-partner:31438
TEST=none yet

Change-Id: I40e5d8b651102709118878a317f7e983a617f433
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a41853273ef9ae716d5645379fcef79c5771b87
Original-Change-Id: I41f03ea8c8104ba2dd9f532b084696385d29636c
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/207973
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8769
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 15:35:06 +01:00
Vadim Bendebury 197b801f19 mips: fix bootblock stack definitions
Bootblock stack on Danube should be SRAM and defined separately from
the rest of the coreboot stack. The actual coreboot stack will be
defined later.

The top of the stack should be above the bottom, as the stack grows
towards lower addresses.

BUG=chrome-os-partner:31438
TEST=ran bootblock on simulator under codescape, observed stack
     properly initialized.

Change-Id: I43d2bae5f85a09a95ca0103b253399bd92555aef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e02724cb4b30990ebaa631dabb45917af29d6437
Original-Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218732
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23 15:34:36 +01:00
Paul Burton cac5022e2f imgvp-danube: Support for the ImgTec Danube Virtual Platform
Add basic board support for the ImgTec Danube Virtual Platform, which
emulates a system built around the Danube SoC.

Run this by loading coreboot.bimg into a flash device connected to SPFI1
chip select 0 & then executing the Danube boot ROM.

BUG=chrome-os-partner:31438
TEST=none yet

Change-Id: Ia62af62804bab261f3cabf7c2e62f5bb08a4a1a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6cb1017f5e2fec85f7f5c60cd2cfec63cc886b49
Original-Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207976
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8766
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 15:34:32 +01:00
Vadim Bendebury f16b0826a0 danube: Use the generic timer interface
Actual timer support is not yet available for Danube, it will be added
soon. For now, just to make the target build, modify it to use
GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option.

BUG=none
TEST=the target builds again

Change-Id: Iad1ceb966d5dbc8687b966be4d2506c8f92eba5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 261837539fb5a31f96e682edbcbbbc0e588f2750
Original-Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220395
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 15:34:27 +01:00
Vadim Bendebury c7b3f727f5 danube: use SOC specific rom stage code
Romstage initialization code does not need to be board specific, keep
it in the SOC directory. Should there be a need for the board specific
code, it can be added later.

BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine

Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3
Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215992
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 15:34:18 +01:00
Furquan Shaikh a252a759c8 t132: Change romstage base address
Romstage was overflowing. So move the base address lower

BUG=chrome-os-partner:31032
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: Ia05034477b51b149c87347ed1880f8e85ecbfbf8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210434
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 14af527a5d7cbb250e2358340196a9d749ec1683)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib261fdd8b4c7eb4a1660c5d02fbcd3e0e3f34b22
Reviewed-on: http://review.coreboot.org/8723
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23 13:16:05 +01:00
Furquan Shaikh 13db0b4679 rush: Add MMC support
BUG=None
BRANCH=None
TEST=Compiles successfully. Depthcharge is able to see mmc.

Original-Change-Id: Ia0c9b432fa447c64fa13e5fae5a66a26bbc86360
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210002
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 4cb05ffa95a2a36c5b4606d2f0efe9e574b84e1d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7f9a27a4c0f0553e78fc1a289bffebbebd37c099
Reviewed-on: http://review.coreboot.org/8716
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23 13:16:01 +01:00
Furquan Shaikh dbf3670977 t132: Add support for tpm i2c
Iniitialize I2C bus required for TPM operation. Problem observed was that if
frequency is raised above 20KHz, TPM starts responding with NAKs either for
address or for data. Need to look into that.

BUG=None
BRANCH=None
TEST=Compiles successfully and TPM success messages seen while booting.

Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210001
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2
Reviewed-on: http://review.coreboot.org/8715
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23 13:15:49 +01:00
Furquan Shaikh e4a642c867 libpayload arm64: Allow board to define upper address limit on DMA
Instead of forcing boards to have DMA region below 4GiB, provide
Kconfig option DMA_LIM_EXCL that a board can use to set the upper
limit in MiB units on the address range reserved by DMA. By default,
this value is 0x1000 i.e. 4GiB limit on the DMA upper address.

BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Default value is seen as 0x1000.

Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3
Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245250
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8800
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23 13:11:24 +01:00
Kenji Chen a874a7c26f PCIe: Revise L1 Sub-State support
BRANCH=None
BUG=None
TEST=Confirmed build pass only
Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: Ic0e845436614e63ad5ace7fb74400f7ea295571c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d3670b92e40d8757a48add6116a0edcec18074d8
Original-Change-Id: I5e029b0f82a771149d4c6127e30b9062e8eaba89
Original-Reviewed-on: https://chromium-review.googlesource.com/244514
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: http://review.coreboot.org/8833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 13:11:18 +01:00
Kenji Chen 31c6e632cf PCIe: Add L1 Sub-State support.
Enable L1 Sub-State when both root port and endpoint support it.

[pg: keyed the feature to MMCONF_SUPPORT, otherwise boards
without that capability fail to build.]

Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092
Original-BUG=chrome-os-partner:31424
Original-TEST=Build a image and run on Samus proto boards to check if the
settings are applied correctly. I just only have proto boards and
need someone having EVT boards to confirm the settings.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a
Original-Reviewed-on: https://chromium-review.googlesource.com/221436
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 13:11:15 +01:00
Patrick Georgi 431e51ec2a libpayload: whitespace cleanup
Align struct members with tabs.

Change-Id: Ie8bdbd718c7217a3f3768dd037fa7c10badbc05e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 18:54:34 +01:00
Aaron Durbin b9894efb86 tegra132: convert to stopwatch API
Simplify the timed operations by using the stopwatch API.

BUG=None
BRANCH=None
TEST=Built and booted to kernel. Analyzed logs. Output as expected.

Change-Id: Ia49bccccc412f23bb620ed386b9174468a434116
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a877020c6d8ba12422c9c2c487122b7eb4a1967b
Original-Change-Id: Iffc32fcb9b8bfdcfbef67f563ac3014912f82e7f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219494
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8831
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 17:01:12 +01:00
Aaron Durbin 43933466e7 exynos: convert to stopwatch API
Instead of open coding monotonic timer usage,
use the stopwatch API.

BUG=None
BRANCH=None
TEST=None

Change-Id: I1c541c1c9f3fde0dec9163ad6cc94322538ac7f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46ede0897687da6bcf730a8904f25e5a4485d6cd
Original-Change-Id: Ia63a05850a1b6afdc42c2422332f77af516d27e3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219716
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8825
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 17:01:04 +01:00
Aaron Durbin 515bd135d2 tegra132: fill out udelay() implementation
There was an empty udelay() implementation result in 0 waits.
Provide an actual implementation.

BUG=None
BRANCH=None
TEST=Built and ran through to depthcharge on rush.

Change-Id: Ia7060566a71c36bb7e4543c2fe4ee49d168518c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8832e73de238358ea801ccd7c2330de35a7b40e
Original-Change-Id: I201f2fdc4e4f5c88d48e4002839b03e808a5a1bc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210827
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 17:00:56 +01:00
Aaron Durbin 53a83fba1e tegra124: switch to stopwatch API
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.

BUG=None
BRANCH=None
TEST=Built, but similar usage tested on tegra132.

Change-Id: I1147f2bed84b93d1b776205df9ae04d1db9c98a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c38e054dd166d5eb53f692833b5ce88a230816e3
Original-Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219712
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8819
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 17:00:48 +01:00
Aaron Durbin 46ba4807e9 device: convert to stopwatch API
Instead of open coding the monotonic timers use the stopwatch
abstraction.

BUG=None
BRANCH=None
TEST=Booted and noted timings work as expected. Built with software_i2c
     and no compilation failures.

Change-Id: Ie5ecdd5bc764c1ab8ba4a923e65a1666aacd22f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7bffb5aeb41e9b88cd2c99edd6abc38f1dc90af
Original-Change-Id: I0170fe4b93d9976957a2dcb00a6ea41ddc0320ce
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219495
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8817
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 17:00:40 +01:00
Aaron Durbin ad5a909740 ramstage: remove rela_time use
mono_time_diff_microseconds() is sufficient for determining
the microsecond duration between 2 monotonic counts.

BUG=None
BRANCH=None
TEST=Built and booted. Bootstate timings still work.

Change-Id: I53df0adb26ae5205e2626b2995c2e1f4a97b012e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: deab836febea72ac6715cccab4040da6f18a8149
Original-Change-Id: I7b9eb16ce10fc91bf515c5fc5a6f7c80fdb664eb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219711
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8818
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 17:00:34 +01:00
Aaron Durbin 4869111443 chromeec: use stopwatch API
Simplify the SPI timeout by using the stopwatch.

BUG=None
BRANCH=None
TEST=Built nyan. Confirmed stopwatch works independently.

Change-Id: Ida26a0748d4b5a6a28aa8f6e2b92fe2ee4cbe17f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 900d7ac826b76d49290033c87849bf776684f2c1
Original-Change-Id: I84b7949060326b7c6cc1872420b93bd44604c4d3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219493
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 17:00:26 +01:00
Aaron Durbin f65153ef07 timer: add stopwatch construct
There's a lot of places where expiration and running time are
open coded. Allow for those places to be simplified by adding
a stopwatch construct. The stopwatch can have an expiration or
just be used to accumulate time.

BUG=None
TEST=Built and verified API works as expected by using implementation.

Change-Id: Ibd636542b16d8554f1ff4512319a53dce81c97e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc623a1b36eb08c5877591c4509cd61131c62617
Original-Change-Id: I53604900fea7d46beeccc17f1dc7900d5f28518b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219492
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8815
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 17:00:17 +01:00
Vadim Bendebury a6b220d8f8 Allow for different BFD elf formats per architecture
The upcoming MIPS toolchain inside chroot generates elf images of
elf32-tradlittlemips format, whereas readily available tools outside
of chroot generate images of elf32-littlemips format. Both of these
formats are perfectly fine, but xcompile accepts only one format per
CPU architecture.

This patch allows to specify multiple formats per architecture, any
matching format will suffice.

BUG=chrome-os-partner:31438
TEST=emerged arm, x86 and mips targets inside chroot

Change-Id: I2c6b8e46b9299059b8e099b93c8c3dcf0a569899
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7f2f1d51643f33b72ac5e4091669f38662e5b9ce
Original-Change-Id: I22405e71ac72b985fad51e2f5d7cc014107b8a9e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214599
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8823
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21 16:57:27 +01:00