Commit Graph

3956 Commits

Author SHA1 Message Date
Patrick Georgi 942c199341 util/abuild: Avoid another git submodule invocation
.xcompile is generated before the submodules handling, but there's no
need for the submodules to be around, so skip here, too.

Change-Id: I60205f65b124a09067de5ae50f066b5cf64733f2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-08-19 20:21:33 +00:00
Elyes HAOUAS 8f1853c4b0 crossgcc: Upgrade LLVM to version 10.0.1
Change-Id: I1d96654fd66a5972c6c5cc24311ca2d889866331
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39921
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18 13:50:02 +00:00
Elyes HAOUAS 9c69369805 crossgcc: Upgrade CMake to version 3.18.1
Release Notes:
  https://cmake.org/cmake/help/v3.18/release/3.18.html

Change-Id: I20b75b7c29be838c3c168547bcab25ea5c1af462
Signed-off-by: Griffin98 <griffin98@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-18 11:43:29 +00:00
Matt DeVillier 5eeead2d73 util/intelp2m: Add support for Cannonlake-LP SoCs
Add support for Cannonlake-LP SoCs (Whiskeylake-U,
Coffeelake-U, Cometlake-U) as a separate parsing profile,
copying the existing 'Sunrise' profile and adjusting for differences
in reset mapping and GPIO macro generation

Test: convert inteltool GPIO log dump into coreboot macros for
an out-of-tree CML-U board.

Change-Id: I86296697ee892af7aa0818fb608b6d68fad2f307
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-18 08:49:27 +00:00
Harshit Sharma ac8e1062cb crossgcc: Enable GCC to get asan shadow offset at runtime
Unlike Linux kernel which has a static shadow region layout, we have
multiple stages in coreboot and thus require a different shadow offset
address. Unfortunately, GCC currently only supports adding a static
shadow offset at compile time using -fasan-shadow-offset flag.

For this reason, we enable GCC to determine asan shadow offset address
at runtime using a callback function named __asan_shadow_offset().
This supersedes the need to specify this address at compile time. GCC
then makes use of this shadow offset to protect stack buffers by
inserting red zones around them.

Some other benefits of having this GCC patch are:
a. We can place the shadow region in a separate linker section with
   all its advantages like automatic fit insurance. This ensures if
   a platform doesn't have enough memory space to hold shadow region,
   the build will fail. (However, if we use a fixed shadow offset on a
   platform that actually doesn't have enough memory, it may still
   build without any errors.)
b. We don't modify the memory layout compared to the current one, as
   we are placing the shadow region at the end of the space already
   occupied by the program.
c. We can be much more flexible later if needed (thinking of other
   stages like bootblock).
d. Since we are appending the shadow buffer to the region already
   occupied, we make efficient use of the limited memory available
   which is highly beneficial when using cache as ram.

Further, we have made sure that if you compile you tree with ASan
enabled but missed this patch, it will end up in the following
compilation error:
"invalid --param name 'asan-use-shadow-offset-callback'"
So, you cannot accidentally enable the feature without having your
compiler patched.

Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-17 09:03:19 +00:00
Elyes HAOUAS d592909014 crossgcc: Upgrade IASL to version 20200717
Summary of changes: https://acpica.org/node/183

Change-Id: Ib325fa5c37c32702c572ab56c99e1f8f785cbe53
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17 07:07:33 +00:00
Elyes HAOUAS 384e2c9218 crossgcc: Upgrade Python to version 3.8.5
Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:56 +00:00
Elyes HAOUAS 2574590f8c crossgcc: Upgrade nasm to version 2.15.03
Change-Id: I4b38595cef72053f82216df43f3667abed4c1989
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42855
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:36 +00:00
Elyes HAOUAS a15a7a5c13 crossgcc: Upgrade binutils to version 2.35
Using "MAKEINFO = @MAKEINFO@", it fails to compile, so
binutils-2.35_no-makeinfo.patch will change that to "MAKEINFO = true"

Change-Id: I0ad01e5da34c96fee6a9b1a63897a9fb28471c75
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38666
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:11 +00:00
Elyes HAOUAS 150c438334 crossgcc: Update MPFR to version 4.1.0
Changes: https://www.mpfr.org/mpfr-current/#changes

Change-Id: I1df2c952229056b44d4c618cebe774ea27b55bd1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:04:14 +00:00
Elyes HAOUAS e541268b0a crossgcc: Upgrade GMP to v6.2.0
gmp_freebsd-configure.patch is integrated in upstream so we don't need
it anymore.
Changes: https://gmplib.org/gmp6.2

Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38465
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:03:11 +00:00
Subrata Banik 46f8073249 util/ifdtool: Add Alderlake platform support under IFDv2
Change-Id: Ief8ab6ad280d8a2625404c19d57cd2a24f23cf13
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39533
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01 06:55:25 +00:00
Subrata Banik a717e2f896 util/ifdtool: Make JSL platform entry for lock_descriptor
Change-Id: Ia2ddb4eceab29810b22766a0f241ba4b11e79538
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44057
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01 06:54:51 +00:00
Rob Barnes ce036bd176 util/apcb: Strip SPD manufacturer information
Strip manufacturer information from SPDs before injecting into APCB.
This allows more flexibility around changing DRAM modules in the future.

BUG=b:162098961
TEST=Boot, dump memory info

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-29 09:35:05 +00:00
Maxim Polyakov 82ec61e9d7 util/intelp2m: Add Intel Pad to Macro utility
This patch adds a new utility for converting a pad configuration from
the inteltool dump to the PAD_CFG_*() macros [1] for coreboot and GPIO
config data structures for FSP/sdk2-platforms/slimbootloader [2,3].
Mirror: https://github.com/maxpoliak/pch-pads-parser.git

[1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
[2] https://slimbootloader.github.io/tools/index.html#gpio-tool
[3] 3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h

Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35643
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 22:06:02 +00:00
Peter Lemenkov 21f01c5a53 intelvbttool: Fix some typos in error messages
Change-Id: Id6298883c39c21179b13696dab630818b81026ff
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43905
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 19:20:05 +00:00
Martin Roth a020903307 util/lint/Kconfig_lint: Update Naked BOOL reference to error
The lint-stable makefile target only watches for errors in the Kconfig
file, so has not protected additional "Naked" references to BOOL type
Kconfig symbols from entering the tree.  Update it to an error so that
they can't continue coming into the codebase.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icce2a9a627c4fbcaa220df18474cb8bfea8b2a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27 05:07:51 +00:00
Benjamin Doron 552ce003a5 util/inteltool/gpio_names: Make group and community titles consistent
Consistency is good for scripting and automation.
The lowercase "group" in Sunrise Point-LP, for example, was
breaking pattern matching used in intelp2m.

Change-Id: Iffa8a8ac9c17c5cbd8d7b838d9c703cae6a858b5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:48:48 +00:00
Paul Menzel 56642930ab mb/lenovo: Prepend EC event number with 0x to denote hex notation
Currently, the message below is printed, suggesting it’s decimal
notation:

    coreboot-4.12-1530-g7acbd5fc45 Sun Jul 19 07:47:58 UTC 2020 smm starting (log level: 7)...
    EC event 48
    GPI (mask 1000)

Prepend 0x, so it’s clear it’s hexadecimal notation.

    EC event 0x48

Use the command below change all places:

    git grep -l 'EC event %02x' | xargs sed -i 's/EC event %02x/EC event %#02x/'

Change-Id: I8d1e6434a0e550c5a19576f9f7fea05e7a812e49
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:40:16 +00:00
Rob Barnes 4d2db06ab5 util: Remove extra newlines in log messages
Print adds a newline implicitly. Simply remove the extra newlines.

BUG=None
TEST=Build zork, observe build log

Change-Id: Idb150c12c90719ba1465e7e7fe45c26d456e2a1c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43786
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:16:35 +00:00
Peter Lemenkov f04b262710 autoport: Don't initialize already initialized fields in acpi_tables
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. Also add some comments.

See also these commits:

* Commit a76cf28 with Change-Id
  I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682 ("mb/lenovo/*/acpi_tables:
Don't initialize already initialized fields").
* Commit 0c52638 with Change-Id
  I71f092ed7582b4931122d72f41d0b42a7569b96e ("mb/lenovo: Remove
thermal.h header").

Change-Id: I1a0042bc93a2b30babcb896b3df23faf37998f3c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40479
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:14:10 +00:00
Jan Dabros ffa58cfc12 util/lint: Add lint and checkpatch coverage for tests/ dir
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I8018b75844e630c9ed46c8bc48f2aa1634bf3369
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26 21:11:05 +00:00
Matt Papageorge be4376c6c6 util/amdfwtool: Add support for EFS SPI values for F17h and F15h
The Embedded Firmware Structure contains various SPI parameters for
the PSP to program. This change adds support to amdfwtool for
populating these values as well specifying SOC Family and Model.

BUG=b:158755102
TEST=Read EFS values at appropriate offsets using a hex editor. Boot
test on Tremblye and Morphius.

Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:06:10 +00:00
Angel Pons a29f9e51b0 */mb/google/volteer/**/gpio.h: Fix up license header
There's a `GPL-2.0-or-later` version of this file in volteer2, so use it
in place of these weirdly-licensed files.

Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-26 20:55:19 +00:00
Elyes HAOUAS e65280cbef autoport/bd82x6x.go: Remove generated extra line
Change-Id: I48125b7efd599b6a6718d7353156217df874d490
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:16:58 +00:00
Tim Wawrzynczak ac2282e907 util/mb/google/volteer: Delete dptf.asl
Since we are not using raw ASL files anymore for DPTF, delete the
template file too, so that it does not keep getting added for new
board variants.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia128989c64b8c02759c326431b4ee30fd2b483e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-24 23:27:39 +00:00
Maxim Polyakov de7092b8a3 inteltool/gpio: Add support for new Lewisburg chipsets
- Add SKUs and Super SKUs of new Lewisburg series chipsets:
  C621A, C627A, C629A [1].
- These changes allow the utility to generate the GPIO config
  registers dump.

[1] https://review.coreboot.org/c/coreboot/+/40395

Change-Id: I9b63c0a3860a901e58af0c0d5184361661bab5e3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43534
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 16:40:48 +00:00
Maxim Polyakov ec0551c6b0 util/inteltool: add missing L0 and L1 pads for Lewisburg
The description for L0 and L1 was missed in the datasheet, however,
configuration registers for these pads are present. In addition, the
chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT"
pads in a circuit diagram. Use all available information to add a
description for the missed pads.

Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 16:39:14 +00:00
Paul Fagerburg 31b7d95350 util/mb/google: add template files for dalboz and trembyle
Now that Zork is using upstream coreboot, we need the template files
in the main branch.

BUG=b:157570490
TEST=n/a

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I6cab4ab0b414473e0a759dce81df9872a40d3f26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43419
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 20:45:03 +00:00
Paul Menzel df5571dc9d util/board-status: Reject logs with unknown timestamps
Check the output of `cbmem -t` for unknown timestamps. If present, ask
the user to rebuild `cbmem`.

Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-15 12:31:46 +00:00
Evgeny Zinoviev 7c1fe4bd12 util/intelmetool: Fix error message
Add a missing space to the message.

Change-Id: I7d4042ebb587af8558294fb4961100b43910fd4a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-15 08:33:55 +00:00
Idwer Vollering 66dcda9e15 util/inteltool: add PCI ID for ICH10DO
Change-Id: I3561679ef50f4c094d2503539074c957f759ecef
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 21:54:33 +00:00
Patrick Georgi 793bf7e605 util/xcompile: Look for the host compiler in XGCCPATH, too (and first)
If there's a host compiler in XGCCPATH, it's likely the same
relatively-current version we use for coreboot, and it's a well-known
quantity, so let's prefer that over alternatives by default.

In addition, look for the C++ host compiler as well.

Change-Id: If50341df169a476899b5a5ffd4c4fb6d21c3f4ac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 08:53:41 +00:00
Patrick Georgi f2741aa632 util/crossgcc: Always bootstrap for gcc < 4.9
Building cbfstool requires at least 4.9 due to optimizer bugs in gcc
3.x to 4.8.x, so let's not work around ancient compilers in our tree
but ensure that users get a newer compiler.

Closes: https://ticket.coreboot.org/issues/240
Change-Id: I4e0f80e2790514e6a1b5d5de1a373f365df1569c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43143
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:45:40 +00:00
Benjamin Doron c01fa5ad5d util/inteltool: Support dumping more BARs on Skylake mobile SoCs
Support dumping MCHBAR, EPBAR, DMIBAR and PCIEXBAR on SKL-U/Y.
These chipsets are similar to others supported by the tool.

Working on SKL-U.

Change-Id: Ic43d54ef189d500701872a56e67781a744990328
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-07 08:56:13 +00:00
David Wu d964fea5a6 lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL:
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E

BUG=b:159195585,b:152936481,b:156435028
TEST=build.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-07-07 04:18:55 +00:00
Patrick Rudolph 7d28f20051 pgtblgen: Update comment to match what the code does
Change-Id: Ib87c804b139a96a4173a6f392f0f99a77d32fc01
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-06 17:24:59 +00:00
Kyösti Mälkki b2a10f8264 devicetree: Remove weak declarations for ops
Make it compulsory to build with all the drivers that are
visible in the board devicetree.cb file.

Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-06 16:11:02 +00:00
Edward O'Callaghan d0089c2b07 util/tmpl/puff: Allow USB2/3 wakeups to (un)plug events
BUG=b:159187889
BRANCH=none
TEST=none

Change-Id: Ib59108ec42955b5414f76b591cce5073f7dad1a9
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42990
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 00:02:55 +00:00
Patrick Georgi 8edfddcb54 util/futility: Check for pkg-config and libcrypto
When building a configuration that requires futility (e.g. Chrome OS
builds), pkg-config and libcrypto are required. Since vboot's build
system isn't the most helpful about it, test ourselves and fail out
with some actionable message.

Tested:
 - configs that don't need futility don't test for pkg-config, so it's
   not required for them.
 - failing pkg-config test leads to the message
 - working pkg-config test leads to a successful build

Fixes https://ticket.coreboot.org/issues/242

Change-Id: I103ce5115284352e0a3a7fdcf8b427f56ce15ba7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-01 18:12:05 +00:00
Patrick Georgi c6dd4435d2 util/cbfstool: Defuse vboot's openssl linking
Vboot determines openssl through pkgconfig, so pointing its build
system to /bin/true makes the build not break unless it needs to use
valid information about openssl.

Vboot's use of openssl is only for some special features, mostly around
PKCS key format parsing and not needed by cbfstool. While cbfstool
can link vboot, it can't link with openssl because openssl's license
is deliberately incompatible with the GPL.

Change-Id: Ia3825f9625a1964d7cefc47ab3c3a8250ceefafb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-07-01 18:06:16 +00:00
Elyes HAOUAS 157851fdbb crossgcc: Upgrade IASL to version 20200528
Update fixes build issues with host GCC 10.

Other changes:
  https://acpica.org/node/177
  https://acpica.org/node/178
  https://acpica.org/node/179
  https://acpica.org/node/181

acpinames utility removed:
"Removed support for the acpinames utility. The acpinames was a simple
utility used to populate and display the ACPI namespace without executing
any AML code. However, ACPICA now supports executable opcodes outside of
control methods. This means that executable AML opcodes such as If and
Store opcodes need to be executed during table load. Therefore, acpinames
would need to be updated to match the same behavior as the acpiexec
utility and since acpiexec can already dump the entire namespace (via the
'namespace' command), we no longer have the need to maintain acpinames."

Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38907
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 12:28:41 +00:00
Kyösti Mälkki 0c1dd9c841 ACPI: Drop typedef global_nvs_t
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.

Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30 09:19:10 +00:00
Julius Werner bc1cb38ce1 Add qc_blobs repository
This patch adds a separate blobs repository for Qualcomm blobs,
analogous to the existing AMD blobs. Qualcomm's binary licenses allow
files to be redistributed and used by anyone, but they explicitly
require the user to agree to the license terms when just *downloading*
the binary (even if they're not using them to build any firmware). Some
community members do not like to have to agree to licenses for files
they're not actually using, so we are keeping these files separate from
the main blobs repository and adding an extra Kconfig to make sure the
user is aware of and must explicitly agree to this before downloading
these files.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30 08:57:03 +00:00
Stefan Reinauer 88e54e38d4 Fix up Docker paths to match jenkins nomenclature
Jenkins is calling its build nodes "agent". Reflect that in
the path names we use in configuration.

Change-Id: I88a4d3d32a565ade768e3de6428f46d355bedfb2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42819
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26 18:56:48 +00:00
Patrick Georgi b9d0c0f7a3 util/abuild: Only update submodules once
Without this, each build will try to update the submodules. Not
necessarily a problem but git locks repos, creating spurious error
messages.

Change-Id: Iba20677d4b5f9365c92f7ed247ca56acb7d33b27
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25 16:59:19 +00:00
Zhuohao Lee 36aaddf7d7 util/mainboard/google/volteer: Add dptf.asl to the template
The dptf.asl is needed when creating a new volteer variant, otherwise,
it will make the variant build failed. The error could be found from
this link: https://review.coreboot.org/c/coreboot/+/42709

BUG=b:158797761
TEST=Generate the Delbin correctly

Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Ib4059df9e08d6a1dba88f0299bb39c8c6ae406ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-24 05:07:27 +00:00
Edward O'Callaghan 5d33d03d3f util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB ports
Switch USB2 port1 and port3 due to circuit change from rev0.

BUG=b:154071868,b:154585046,b:156429564
BRANCH=none
TEST=none

Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 01:15:14 +00:00
Edward O'Callaghan b6737fc54a util/mb/google/tmpl/puff: Import overridetree.cb copy
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 01:13:12 +00:00
Edward O'Callaghan 4229dfc215 util/mb/google/tmpl/puff: Generate correct gpio muxing
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: Iae4fe48b6a3df730b2334cb1f32b35addc90bec0
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 00:06:56 +00:00