Commit Graph

20244 Commits

Author SHA1 Message Date
Gwendal Grignou 87d5fb89fe ec/google/chromeec: Add support for tablet mode switch driver
Add a new driver GOOG0006 to report tablet switch
to user space.

On glados based convertible, check that with a new kernel driver
(cros_ec_tbmc) that evtest collects tablet switch changes.

Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430951
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/18173
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-07 01:44:52 +01:00
Kyösti Mälkki 3d3c8c30ea devtree: Drop unused parameter show_devs_tree() call
Change-Id: I14c044bb32713ef4133bce8a8238a2bc200c4959
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18085
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-06 20:22:01 +01:00
Martin Roth 8e4aafb531 src/Kconfig: Move options with no prompt towards the end of the file
Options with no prompt can go anywhere in the tree with the same
dependencies and they have the same effect.  Moving them lower in
the tree allows the default values to be overridden by other Kconfig
files.

This patch just moves options with default values that aren't 'n'. The
'n' options are just removed in the next patch, since they aren't needed.

Verified that this makes no significant changes to any config file.

Change-Id: I46175756b937a241edba87dbf70ce1be851fa89d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17907
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-06 20:14:45 +01:00
Duncan Laurie 649100ad20 google/eve: Fix keyboard backlight enable in wake from G3
The WAK_STS bit is not set in a wake from G3, so the check for this
bit needs to only be done when checking for a wake from S3.

This change correctly enables the keyboard backlight in wake from G3
and only does not enable it during a wake from S3.

BUG=chrome-os-partner:58666
TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard
backlight turns on like it does when waking from S5.  Also force enter
hibernate with Alt+VolumeUp+H and then power back up and ensure that
the keyboard backlight is enabled when booting.

Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18280
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-05 22:01:50 +01:00
Martin Roth 75e5cb7a74 src/Kconfig: Move early defaults to the end of the file
For Kconfig options that we might want to override the default,
move the fallback default to the bottom of the file.  This allows
the default to be set anywhere else, without requiring a select.

This is especially important for non-boolean symbols, which can't
have their defaults overridden in the Kconfig.  Those can only be
updated in a saved config file.

Verified that this makes no significant changes to any config file.

Change-Id: I66034f356428f4ccd191d7420baf888edd5216dc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-04 23:19:19 +01:00
Damien Zammit 0685322f4a util/blobtool: Add new tool for compiling/decompiling data blobs
Given a specification of bitfields defined e.g. as follows:

	specfile:
		{
			"field1" : 8,
			"field2" : 4,
			"field3" : 4
		}
and a set of values for setting defaults:
	setterfile:
		{
			"field1" = 0xff,
			"field2" = 0xf,
			"field3" = 0xf
		}

You can generate a binary packed blob as follows:
	./blobtool specfile setterfile binaryoutput
	binaryoutput:	ff ff

The reverse is also possible, i.e. you can regenerate the setter:
	./blobtool -d specfile binaryoutput setterorig
	setterorig:
		# AUTOGENERATED SETTER BY BLOBTOOL
		{
			"field1" = 0xff,
			"field2" = 0xf,
			"field3" = 0xf
		}

This tool comes with spec/set files for X200 flash descriptor
and ICH9M GbE region, and can be extended or used to decompile
other data blobs with known specs.

Change-Id: I744d6b421003feb4fc460133603af7e6bd80b1d6
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17445
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04 23:18:35 +01:00
Matt DeVillier aaa4ae766d google/jecht: Fix LED for guado/rikku variants
When guado/rikku/tidus were rolled into jecht, an error was
made in set_power_led() as guado/rikku set the polarity
differently than tidus.  Fix the power LED for guado/rikku
by setting the polarity correctly.

Test: boot guado/rikku and observe proper function of power LED
under S0, S3, and S5 power states.

Change-Id: I23072ac60bc9683776f748ca1326d98257c3c54f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18249
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04 23:15:12 +01:00
Francis Rowe 3054ca164e lenovo/x60: use correct BLC_PWM_CTL value
Bit 16 in BLC_PWM_CTL enables brightness controls, but the
current value is generic. Use the proper value, obtained
by reading BLC_PWM_CTL while running the VBIOS.

Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: https://review.coreboot.org/10624
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-04 23:11:46 +01:00
Kevin Chiu b576e6f236 Revert "google/pyro: remove Wacom touchscreen probed flag"
Reason for revert:
Pyro has two touchscreen sources: WACOM/ELAN.
It will not have both touchscreen IC in one system at the same time.

So the "probed" property of WACOM i2c device is mandatory to set for kernel
to know whether it exists before driver initializes it.

Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF
will be invoked to set GPIO#152 low to cut off power.

BUG=chrome-os-partner:62371
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-04 23:09:29 +01:00
Arthur Heymans 410f256b6f Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implemented
This also selects RELOCATABLE_RAMSTAGE and
CACHE_RELOCATABLE_RAMSTAGE_OUTSIDE_CBMEM by default on Haswell.

Change-Id: I50b9ee8bbfb3611fccfd1cfde58c6c9f46b189ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18232
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-04 23:08:38 +01:00
Duncan Laurie 9471d00a4f google/eve: Fix DRAM DQS map
This change fixes the two sets of pins that were swapped in the
map of DQS signals from CPU to DRAM for channel 1.

Although this does not appear to have any impact to the system it
does result in different register values for DQS pin mapping that
are programmed inside FSP.

BUG=chrome-os-partner:58666
TEST=This fix was verified against the current schematic and using
FSP debug output.

Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18279
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-04 23:05:23 +01:00
Nico Huber 561bebfbaa drivers/intel/gma/vbt: Add Kconfig symbol for SSC ref
The selection of the SSC reference frequency for LVDS was based on a
completely unrelated clock.

The `ssc_freq` flag should be set when the SSC reference runs at a
different frequency than the general display reference clock (DREF).
For most platforms, there is no choice, i.e. for i945 and gm45 the SSC
reference always differs from the display reference clock (i945: 66Mhz
SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and
newer, it's the same frequency for SSC/non-SSC (120MHz).  The only,
currently supported platform with a choice seems to be Pineview, where
the alternative is 100MHz vs. the default 96MHz.

Change-Id: I7791754bd366c9fe6832c32eccef4657ba5f309b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04 23:04:06 +01:00
Rizwan Qureshi 84394616df google/poppy: Set GPIO GPP_D22 high
same change as I49935e659bf67225d3f5db1b06acc2cd046dcd74
this is required for poppy board as well.

GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals
when doing GPIO-driven I2S.  This needs to be high by default so
the DSP can drive these signals, instead of low where it is enabled
for GPIO-driven I2S and the DSP cannot drive these signals.

BUG=None
BRANCH=None
TEST=play test sound in OS over internal speaker

Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18282
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-04 23:03:40 +01:00
Duncan Laurie 5de37d5d7a google/eve: Set GPIO GPP_D22 high
GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals
when doing GPIO-driven I2S.  This needs to be high by default so
the DSP can drive these signals, instead of low where it is enabled
for GPIO-driven I2S and the DSP cannot drive these signals.

BUG=chrome-os-partner:58666
TEST=play test sound in OS over internal speaker

Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18281
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-04 23:03:22 +01:00
Nicola Corna 92e95cab96 sb/intel/common: Hook up me_cleaner
The me_cleaner option is available on multiple platforms:
 * Sandy and Ivy Bridge (well tested by multiple users).
 * Skylake and Braswell (tested).
 * Haswell, Broadwell and Bay Trail (untested).

The untested platforms have been included anyways because all the
firmwares are very similar and Intel ME/TXE probably behaves in the
same way.

Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18206
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04 23:02:39 +01:00
Patrick Rudolph bb1af99622 nb/intel/gm45/igd: Hide IGD while disabling
Hide the IGD to make sure ramstage doesn't detect it.

Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18194
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-04 23:01:55 +01:00
Patrick Rudolph a5c2ac6256 x86/acpi: Add VFCT table
Add VFCT table to provide PCI Optiom Rom for
AMD graphic devices.
Useful for GNU Linux payloads and embedded dual GPU systems.

Tested on Lenovo T500 with AMD RV635 as secondary gpu.

Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>

Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Reviewed-on: https://review.coreboot.org/18192
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04 23:01:37 +01:00
Patrick Rudolph 8a06cc7ec8 util/ifdtool: Fix ICH Gbe unlock
With coreboot 4.4 switched to "Descriptor mode" for Lenovo T500
it automatically unlocks all flash regions. For Gbe region
the "Requester ID" was hardcoded resulting in *dead* Gbe.

Keep board specific "Requester ID" while unlocking Gbe region.

Allows Lenovo T500 to boot with IFD "Descriptor mode" with unlocked
flash regions.

Signed-off-by: Patrick Rudolph <siro@das-labor.org>

Change-Id: Ia4b5d1928e84bee42182fc83020e3a13fadc93c4
Reviewed-on: https://review.coreboot.org/18055
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-02-04 17:36:21 +01:00
Harry Pan 4a282b8419 mainboard/google/snappy: Set PL2 override to 15000mW
This patch sets PL2 override value to 15W in RAPL registers.

BUG=chrome-os-partner:62110
BRANCH=reef
TEST=Apply new firmware to evaluate Octane benchmark score.

Change-Id: I51734051586753677129314b5273fb275c74f5d2
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/18283
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-02-03 15:36:27 +01:00
Arthur Heymans 84e6881ba5 mb/lenovo/x60,t60: Move EC CMOS parameters in checksummed space
This allows for defaults to be applied to CMOS parameters
when cmos checksum is incorrect.

This probably results in changed cmos settings for current users of
these targets.

Change-Id: Ifec0093f4b0dbaa51b96812a041f0eaf5c58ee86
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-03 02:03:02 +01:00
Tobias Diedrich 31db6f5e17 asus/f2a85-m_le: Activate IOMMU support
Activate the IOMMU for the ASUS F2A85-M LE board.

Enable the IOMMU in `devicetree.cb` and build AGESA IOMMU code by
enabling the option in `buildOpts.c`.

ACPI and MPTABLES interrupt routers are already present since they are
syminks to the F2A85-M version.

```
$ uname -a
Linux nukunuku 4.8.5 #35 SMP Sun Oct 30 19:34:55 CET 2016 x86_64 GNU/Linux
$ lspci -s 0.2
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit
$ dmesg | grep -i IOMMU
ACPI: IVRS 0x00000000BFFAFF70 000070 (v02 AMD    AMDIOMMU 00000001 AMD  00000000)
AMD-Vi: Applying erratum 746 workaround for IOMMU at 0000:00:00.2
iommu: Adding device 0000:00:01.0 to group 0
[...]
iommu: Adding device 0000:00:18.5 to group 9
iommu: Adding device 0000:03:00.0 to group 8
AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40
AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>
```

Change-Id: I6049fcfad53d16a99495d7a8fbc584c71e371d73
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/18259
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-03 02:02:38 +01:00
Steven Dee 3236f7be09 ectool: Support OpenBSD
Adds checks for OpenBSD in all the places that were already checking for
NetBSD. This fixes e.g.:

    ec.c:21:20: error: sys/io.h: No such file or directory

which was caused by defaulting to Linux.

Also, OpenBSD calls its amd64 iopl amd64_iopl instead of x86_64_iopl.
This change just defines iopl appropriately depending on the
OS and architecture.

TEST=Build on OpenBSD 6.0 or -current from 2017-01-25.

Change-Id: If6d92a9850c15cd9f8e287cc4f963d3ff881f72c
Signed-off-by: Steven Dee <i@wholezero.org>
Reviewed-on: https://review.coreboot.org/18260
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-02 15:29:10 +01:00
Mario Scheithauer 092db95742 siemens/mc_apl1: Add new mainboard
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with minimum changes. Special adaptations for MC APL1
mainboard will follow in separate commits.

Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18272
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
2017-02-02 07:06:20 +01:00
Marshall Dawson fc18507134 payloads/depthcharge: Allow generic libpayload config
Change depthcharge to not require a board-specific config file for
libpayload.  If the Kconfig option is selected, use the settings
in libpayload/configs/defconfig instead.

Change-Id: I4fd1a5915472f28e757c62f3f2415716f1fdfc71
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18271
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01 21:14:29 +01:00
Matt DeVillier 9be3f5dab4 Add Baytrail ChromeOS devices using variant scheme
Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty,
heli, kip, orco, quawks, squawks, sumo, swanky, and winky using
their common reference board (rambi) as a base.

Chromium sources used:
firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...]
firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...]
firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...]
firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...]
firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...]
firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...]
firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*]
firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.]
firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data]
firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data]
firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...]
firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table]
firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...]

The same basic cleanup/changes are made here as with the initial BYT
variant commit:
 - remove unused ACPI trackpad/touchscreen devices
 - correct I2C addresses in SMBIOS entries
 - clean up comment formatting
 - remove ACPI device for unused light sensor
 - switch I2C ACPI devices from edge to level triggered interrupts,
   for better compatibility/functionality (and to be consistent
   with other recently-upstreamed ChromeOS devices)
 - Micron 2GB SPD file for kip with updated values renamed to distinguish
   from same file used by other boards

Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18164
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01 21:14:13 +01:00
Marshall Dawson f9973b5c2b payloads/depthcharge: Specify revision to build
Add the capability for specifying which version of depthcharge to
checkout and build.  This is similar to the existing feature for
SeaBIOS.

The depthcharge makefile already contains some structure for checking
out master vs. stable however the calling Makefile.inc ingored this
feature.  Add the command-line variable assignment for these, along
with a tree-ish for any revision.

Change-Id: I99a5b088cb0ebb29e5d96a84217b3bfa852de8ac
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18270
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01 20:15:04 +01:00
Marshall Dawson 8f470c7a7e payloads/depthcharge: Use variable target name
Depending on the commit to build, depthcharge may have a different
target name (depthcharge vs. depthcharge_unified).  Add some logic
to determine which name should be used based on the commit ID
being requested.

Change-Id: I05b853934d13696f4bd0d79d53ff6c5f59096d1c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18269
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01 20:14:53 +01:00
Marshall Dawson 9e33e27a46 payloads/depthcharge: Change make target from unified
Drop the _unified moniker from the depthcharge build.  The payload
and coreboot have drifted out of sync and there is no longer a
non-unified depthcharge.

This patch corresponds with the depthcharge change:
https://review.coreboot.org/cgit/depthcharge.git/commit/?id=74a0739

Change-Id: I8d028b14d2eee63dfdc9d3dd63695f1c58ea7984
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18268
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01 20:14:26 +01:00
Patrick Georgi c09e148b38 google/veyron*: mark GPIO array non-static
That status isn't needed and making it non-static helps gcc 4.9.2 (or
any compiler that insists on "standard C" behaviour with global const
initializers)

Change-Id: Ib1fbd5213d262e653f31564b106095b4a28292f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/18266
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-31 19:21:22 +01:00
Patrick Georgi 78a5f22994 build system: mark sub-make invocations as parallelizable
We rely on gnu make, so we can expect the jobserver to be around in
parallel builds, too. Avoids some make warnings and slightly speeds up
the build if those sub-makes are executed (eg for arm-trusted-firmware
and vboot).

Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/18263
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-31 18:51:55 +01:00
Patrick Georgi be182ad380 util/xcompile: parallelize compiler checks
Speed up the execution of this script from ~6 seconds to ~1 on my
system.

There are some changes to its output, but they're actually _more_
correct: so far, architectures without compiler support kept compiler
options for architectures that ran successfully earlier.

Change-Id: I0532ea2178fbedb114a75cfd5ba39301e534e742
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/18262
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-31 18:51:47 +01:00
Paul Menzel 7328cf948e asus/m2v,m2v-mx_se: Unify Kconfig
Reorder the items to minimize the differences.

Change-Id: I745ec70a990f997d87c2a0b6164ae127eb694ddf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17438
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-31 17:45:17 +01:00
Martin Roth 8e4bb3164a src/lib: Update Makefile to keep build/spd.bin rule private
The rule to make spd.bin that's in src/lib is for the 'generic_spd_bin'
implementation.  It wasn't guarded though, so it was generating a build
warning for any other platform that generated an spd.bin file.

Sample warning that this fixes:
src/mainboard/gizmosphere/gizmo/Makefile.inc:42:
warning: overriding recipe for target 'build/spd.bin'
src/lib/Makefile.inc:298: warning: ignoring old recipe for target
'build/spd.bin'

Change-Id: Iadd6743f8ae476969bf36f99b918f04c04172d1d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/18261
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-31 17:44:24 +01:00
Sathyanarayana Nujella 545edca577 mainboard/google/reef: remove NHLT DMIC 1ch and 2ch configuration
Apollolake boards should use DMIC-4ch configuration in Kernel side and
use CaptureChannelMap in userspace to distinguish boards with different
number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will
not be required and hence removed.

BUG=chrome-os-partner:60827
TEST=Verify internal mic capture
TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works

Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/18252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-31 15:17:53 +01:00
Vaibhav Shankar 6e5609124e mainboard/google/reef: Set edge triggered interrupt for GPIO_22
EC sets the logic level based on outstanding wake events. When GPIO_22
is configured as a level triggered interrupt, the events are not
cleared from the interrupt handler. Hence, we'd just be re-signalling
over and over causing an interrupt storm upon lid open. So, GPIO_22
needs to be configured as EDGE_SINGLE instead of LEVEL.

BUG=chrome-os-partner:62458
TEST=Lid close/open. check CPU usage using top. It should
not show 70% CPU usage.

Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>

Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a
Reviewed-on: https://review.coreboot.org/18267
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-31 15:17:38 +01:00
Furquan Shaikh 775765eaf3 vboot: Add mock functions for recovery space read/write
For the boards that intend to use mock tpm and have recovery mrc cache
support enabled, provide mock functions to read and write mrc hash
space.

Reading MRC hash space returns TPM_SUCCESS as later checks take care of
comparing the hash value and retraining if hash comparison fails. Thus,
in case of mock tpm, device would always end up doing the memory
retraining in recovery mode.

BUG=chrome-os-partner:62413
BRANCH=None
TEST=Verified that eve builds with mock tpm selected.

Change-Id: I7817cda7821fadeea0e887cb9860804256dabfd9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18248
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-30 17:45:36 +01:00
Furquan Shaikh f8ab456a63 mainboard/google/snappy: Update WDT touchscreen device
Export PowerResource for WDT touchscreen device.

BUG=chrome-os-partner:62311, chrome-os-partner:60194,
chrome-os-partner:62371
BRANCH=reef
TEST=Compiles successfully.

Change-Id: Icc5be170353753201d3571c39b50e29424d4d6d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18240
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-29 21:32:42 +01:00
Furquan Shaikh a7a517ddc5 mainboard/google/pryo: Update touchscreen device ACPI nodes
1. For ELAN, export reset GPIO as well as PowerResource
2. For WCOM, export PowerResource

BUG=chrome-os-partner:62311, chrome-os-partner:60194,
chrome-os-partner:62371
BRANCH=reef
TEST=Verified that touchscreen works on pyro with WCOM device on
power-on as well as after suspend/resume.

Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18239
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-29 21:32:28 +01:00
Furquan Shaikh 71d830fddc i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPI
Linux kernel expects that power management with ACPI should always be
handled using PowerResource. However, some kernel drivers (e.g. ELAN
touchscreen) check to see if reset gpio is passed in by the BIOS to
decide whether the device loses power in suspend. Thus, until the kernel
has a better way for drivers to query if device lost power in suspend,
we need to allow passing in of GPIOs via _CRS as well as exporting
PowerResource to control power to the device.

Update mainboards to export reset GPIO as well as PowerResource for
ELAN touchscreen device.

BUG=chrome-os-partner:62311,chrome-os-partner:60194
BRANCH=reef
TEST=Verified that touchscreen works on power-on as well as after
suspend-resume.

Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18238
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-29 21:07:22 +01:00
Iru Cai 8bf53a9f4e autoport: add missing parameter for pc_keyboard_init()
This fixes the build for the generated code for boards with PS/2
keyboard, since commit 448e386309 updated the pc_keyboard_init()
function.

Change-Id: I776b49b847985296eaca4af6d6e49ab5d6abbafe
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18242
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-29 00:36:24 +01:00
Vaibhav Shankar f224e836c0 mainboard/google/reef: Set IOSSTATE for trackpad I2C GPIOs
I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during
standby states S3/S0ix. This causes leakage of power. To reduce the
leakage, we have to pull these lines high during S3/S0ix. This is
done by programming the IOSSTATE to HIz. Also note that we are using
the internal pull ups to keep at SOC at 1.8V and the I2C lines are
not floating.

BUG=chrome-os-partner:62428,chrome-os-partner:61651
TEST=Enter S3/S0ix. Measure trackpad power. It should be less
than 4mW. Also I2c lines should be pulled high in S3/S0ix.

Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/18251
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-01-29 00:35:20 +01:00
Martin Roth 8556db35e0 SeaBIOS Kconfig: Update logging
The SeaBIOS and coreboot log levels don't really align, so setting the
SeaBIOS log level to the same as coreboot's isn't really what we want.

- Update default log level to use the default SeaBIOS log level.
- Update the current help text to match the new defaults.
- Add help text for what is displayed at various levels.
- Get rid of separate type & prompt lines.
- Add comments for default seabios level & logging disabled

Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18210
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2017-01-27 19:46:26 +01:00
Martin Roth 20aa043b44 Makefile: Just error out if no .config exists
Currently coreboot runs the 'config' command if no .config file exists.
This isn't what anyone wants, and is particularly frustrating for tools
that automate the build, where the build just hangs waiting for input.

Instead, just show an error message and then exit the build.

Change-Id: If9e0c2c26f8273814518589a2f94c5b00fc4cefe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18245
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-27 19:43:24 +01:00
Arthur Heymans 017b56558f board_status/towiki.sh: Add socket LGA775
Intel Core 2 is not further specified since not all chipsets support
quad cores, which could confuse users.

Change-Id: I86c0a41743fe784f432347fa639d3c26604e058e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18235
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-27 19:42:36 +01:00
Martin Roth 9ee70ce587 util/docker: Update makefile target names
- Use dashes instead of underscores for consistency and to match other
coreboot targets
- Fix a couple of places where old target names were referenced
- Remove double 'help' target from .PHONEY target list

Change-Id: I3b464ebf74653a8cc880e982316fd883757ec728
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/18000
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-27 19:41:05 +01:00
Martin Roth af25fd78e8 util/docker: Update makefile with command to kill docker images
Kill running docker containers before trying to remove images or
containers.

Change-Id: Id2de90edbe5d0dc6ecb906be7101ad9744dbd11e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/17999
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-27 19:40:41 +01:00
Martin Roth 27f3ce6337 board_status/to-wiki: Update bucketize script
- Fix TODO: restrict $1 to allowed values.
- Specifically exclude 'oem' board status directories.
- Exclude any directory that doesn't follow the date format to keep
the script from breaking again in the future if something it doesn't
recognize is pushed.  Just ignore it for the wiki.
- Fix shellcheck warnings.

Change-Id: I2864f09f5f1b1f5ec626d06e4849830400ef5814
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18225
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-27 04:37:33 +01:00
Arthur Heymans 7218a1e754 Only add etc/ps2-keyboard-spinup when not updating an image
Without this motherboards that requires a non zero timeout for ps2
keyboards on SeaBIOS don't build when CONFIG_UPDATE_IMAGE is set.

An alternative way to achieve this file would be to include a cbfsfile
instead of calling cbfstool. That way the file gets updated/added both
both image update and regular build. A difficulty of that approach is
that it needs to convert a decimal to a binary in little endian
representation, which is not a trivial thing to do in a Makefile.

Change-Id: Icafba8d3e279a2e70e607abba81e3dbebfb55e4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18231
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-27 02:09:38 +01:00
Martin Roth 0e7a93fa65 drivers/pc80/rtc: Check cmos checksum BEFORE reading cmos value
If cmos is invalid, it doesn't make sense to read the value before
finding that out.

Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18236
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-26 23:49:44 +01:00
Kevin Chiu 0117924159 google/pyro: Add USB2 phy setting override
In order to pass type A USB2 eye diagram,
USB2 port#0/#1 PHY register will need to be overridden.

port#0:
PERPORTPETXISET = 7
PERPORTTXISET = 1
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0

port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0

BUG=chrome-os-partner:59491
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18229
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-26 19:43:17 +01:00