The Picasso SoC code generates a CRAT ACPI table which is not done for
Cezanne and newer. A significant part of the Picasso CRAT generation
code can likely be moved to the common AMD SoC code and then used in all
SoCs, but this still needs to be checked.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f1ebe74f0376c60396dbd80e64676d1374ed811
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72027
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This changes the alignment of the IVRS table from 8 bytes to 16 bytes
and aligns the ALIB table to a 16 byte boundary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I766260aefcac6876609d6b45202b41a3e9e44385
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The device operations for the CPU bus are identical for all AMD SoCs, so
introduce a common device operations struct for this and use it in all
AMD SoC's chipset devicetrees as ops for the CPU cluster.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id32f89b8a33db8dbb747b917eeac3009fbae6631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The AMD SoCs no longer have a variable position for EFS - it's now fixed
at 0xff020000 - 128KiB into the 16MiB ROM decode region.
It's a little more complex than that because the chip can be larger than
16MiB, and the entire ROM can be decoded if mapped above the 4GiB
boundary, but we don't currently support doing that in coreboot, so this
is enough for now.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I343a875ba9aa8294a090f2eff7b5dfb5e86334f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
0xF8000000 was taken from old platform during phoenix porting, updating
it to 0xE0000000 to make room for 256 pci busses which is required for
usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256
busses are used.
Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Use the common preloader for fsp-s
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This picks up the following changes:
acf73954 phoenix: rename morgana to phoenix
a2c15297 mendocino: Upgrade SMU to 90.35.166
28983855 Update Picasso FSP binaries
This also updates the phoenix fw.cfg file that points to the submodule.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1d04d6232307dc913645a3d60ac3711018e2bdfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the next generation of APUs is officially announced, we can
unmask morgana.
The chip formerly known as Morgana is actually Phoenix.
Surprise!
This patch just changes the name across the entire codebase.
Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
