coreboot-kgpe-d16

Commit Graph

Author	SHA1	Message	Date
Felix Held	4fbab545b2	mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>	2021-06-01 20:37:15 +00:00
Felix Held	c4eb45fa85	soc/amd/picasso: introduce and use chipset device tree The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>	2021-06-01 20:37:04 +00:00
Zheng Bao	795d73c6d8	soc/amd/picasso: Update coreboot UPD variable names to include units Use command below to change the variable globally. sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \ --exclude-dir=build --exclude-dir=crossgcc` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>	2020-11-06 13:02:24 +00:00
Paul Fagerburg	31b7d95350	util/mb/google: add template files for dalboz and trembyle Now that Zork is using upstream coreboot, we need the template files in the main branch. BUG=b:157570490 TEST=n/a Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I6cab4ab0b414473e0a759dce81df9872a40d3f26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43419 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2020-07-15 20:45:03 +00:00

4 Commits