Commit Graph

137 Commits

Author SHA1 Message Date
Stefan Reinauer fd611f9c2c Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.

Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28 00:00:30 +01:00
Patrick Georgi 70c85eab83 build system: Retire REQUIRES_BLOB
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory,
builds failed when all files were configured to point to other sources.

This change modifies the blob mechanism so that cbfs-files can be tagged as
"required" with some specification what is missing.

If the configured files can't be found (wrong path, missing file), the build
system returns a list of descriptions, then aborts.

Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2418
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19 11:00:41 +01:00
Stefan Reinauer a957b7ad21 ARMv7: drop multiboot support
Multiboot is an x86 only thing. Drop support on ARM.

Change-Id: I13fafa464a794206d5450b4a1f23a187967a8338
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2392
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 23:55:34 +01:00
David Hendricks c146d668ef DEBUG_CBFS should not depend on TPM
This seemed to have been introduced in fe422184.

Change-Id: I4f9ecfbec42aa8c0bb8887675a3add8951645b98
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2327
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09 01:46:26 +01:00
Hung-Te Lin ad173ea70b console: Revise serial console configuration names.
The console drivers (especially serial drivers) in Kconfig were named in
different styles. This change will rename configuration names to a better naming
style.

 - EARLY_CONSOLE:
        Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE
        because it also supports non-serial)

 - CONSOLE_SERIAL:
        Enable serial output console, from one of the serial drivers. (Renamed
        from SERIAL_CONSOLE because other non-serial drivers are named as
        CONSOLE_XXX like CONSOLE_CBMEM)

 - CONSOLE_SERIAL_UART:
	Device-specific UART driver. (Renamed from
	CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped)

 - HAVE_UART_SPECIAL:
        A dependency for CONSOLE_SERIAL_UART.

Verified to boot on x86/qemu and armv7/snow, and still seeing console
messages in romstage for both platforms.

Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2299
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08 01:56:15 +01:00
Stefan Reinauer 275fb63832 Don't add another Kconfig special case for Tiano
We don't need a special Kconfig variable anymore
because the FV _is_ the payload, unlike with the
old tianocoreboot implementation.

Change-Id: I349b5a95783e4146e3ab7f926871188cf2021935
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2284
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-02-05 23:37:54 +01:00
Patrick Georgi ed08bcc12d Hook up corebootPkg as Tianocore payload
This unplugs Stefan's PIANO project.

Change Tianocore payload configuration to use corebootPkg.
As argument you have to give it the COREBOOT.FD generated by
the Tianocore build system.

It automatically determines base address and entry point.

Compression setting is honored (ie. no compression if you don't
want), but corebootPkg currently assumes that coreboot is doing
it. Loading a 6MB payload into CBFS without compression will fail
more often than not.

Change-Id: If9c64c9adb4a846a677c8af40f149ce697059ee6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2280
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-04 22:57:20 +01:00
Stefan Reinauer cc5b344662 Project PIANO aka tianocoreboot
This is a Tiano Core loader payload based on libpayload.  It
will load a Tiano Core DXE core from an UEFI firmware volume
stored in CBFS.

Currently Tiano Core dies because it does not find all the UEFI services it needs:

coreboot-4.0-3316-gc5c9ff8-dirty Mon Jan 28 15:37:12 PST 2013 starting...
[..]
Tiano Core Loader v1.0
Copyright (C) 2013 Google Inc. All rights reserved.

Memory Map (5 entries):
  1. 0000000000000000 - 0000000000000fff [10]
  2. 0000000000001000 - 000000000009ffff [01]
  3. 00000000000c0000 - 0000000003ebffff [01]
  4. 0000000003ec0000 - 0000000003ffffff [10]
  5. 00000000ff800000 - 00000000ffffffff [02]

DXE code:  03e80000
DXE stack: 03e60000
HOB list:  03d5c000

Found UEFI firmware volume.
  GUID: 8c8ce578-8a3d-4f1c-9935-896185c32dd3
  length: 0x0000000000260000

Found DXE core at 0xffc14e0c
  Section 0: .text     size=000158a0 rva=00000240 in file=000158a0/00000240 flags=60000020
  Section 1: .data     size=00006820 rva=00015ae0 in file=00006820/00015ae0 flags=c0000040
  Section 2: .reloc    size=000010a0 rva=0001c300 in file=000010a0/0001c300 flags=42000040

Jumping to DXE core at 0x3e80000
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 3E96708
HOBLIST address in DXE = 0x3E56010
Memory Allocation 0x00000003 0x3E80000 - 0x3EBFFFF
FV Hob            0xFFC14D78 - 0xFFE74D77
InstallProtocolInterface: D8117CFE-94A6-11D4-9A3A-0090273FC14D 3E95EA0
InstallProtocolInterface: EE4E5898-3914-4259-9D6E-DC7BD79403CF 3E9630C

Security Arch Protocol not present!!

CPU Arch Protocol not present!!

Metronome Arch Protocol not present!!

Timer Arch Protocol not present!!

Bds Arch Protocol not present!!

Watchdog Timer Arch Protocol not present!!

Runtime Arch Protocol not present!!

Variable Arch Protocol not present!!

Variable Write Arch Protocol not present!!

Capsule Arch Protocol not present!!

Monotonic Counter Arch Protocol not present!!

Reset Arch Protocol not present!!

Real Time Clock Arch Protocol not present!!

ASSERT_EFI_ERROR (Status = Not Found)
ASSERT /home/reinauer/svn/Tiano/edk2/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c(461): !EFI_ERROR (Status)

Change-Id: I14068e9a28ff67ab1bf03105d56dab2e8be7b230
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2154
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 17:34:40 +01:00
Stefan Reinauer d37ab454d4 Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.

See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.

To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.

For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/

Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12 19:09:55 +01:00
Stefan Reinauer 3600e960b6 Fix UART8250 console prototypes
and disable IO mapped UARTs on ARMV7 per default

Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2021
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-12 00:27:10 +01:00
Stefan Reinauer 6edb729cee Drop ARCH_ARM in favor of ARCH_ARMV7
The ARM architecture is really many architectures, and most
of them need their own toolchain. After discussing with Ron
and David, we decided that we're going to call the architecture
of our ARM board armv7.. This patch cleans out the remainders
of ARCH_ARM in the tree and moves on to consistent ARMv7 naming.
As of now, we only support little endian ARMv7 CPUs. We can
fix that for big endian if/when it comes our way.

Change-Id: Id70c7ef615f600e4d09961d811e7ac974fce4811
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06 02:26:42 +01:00
Stefan Reinauer 8d7115560d Rename devices -> device
to match src/include/device

Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1960
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30 23:59:58 +01:00
Ronald G. Minnich 78a1667cbc Create a a new configuration variable for PCI
Not all architectures have PCI. This new config variable allows control
of whether PCI support is configued in. It is selected for ARCH_X86.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1947
Tested-by: build bot (Jenkins)
2012-11-30 19:02:58 +01:00
David Hendricks 5367e47ef1 Add dummy Kconfig options for armv7
This adds a dummy config for ARMV7 for developing various
follow-up patches which rely on ARCH_ARMV7.

Change-Id: Id913054d916f41607d10ebc02aaf74082e14b554
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-11-30 00:03:37 +01:00
Ronald G. Minnich 6e3728bb12 Add .h files for samsung exynos 5250
Per a conversation with Stefan, these chip-dependent files are moved
to the src tree, in the manner of other chips (north and southbridge).

Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Reviewed-on: http://review.coreboot.org/1925
Tested-by: build bot (Jenkins)
2012-11-28 07:55:59 +01:00
Stefan Reinauer 56cd70bba2 Fix Kconfig GENERATE_*_TABLE usage
Some boards selected GENERATE_ instead of HAVE_

Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1841
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16 01:15:55 +01:00
Stefan Reinauer 95a6396ae3 Clean up Kconfig
- move VGA handling options into devices/Kconfig
- make Devices a top level menu
- move some  options "closer" to the code they control

Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1840
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16 01:13:47 +01:00
Stefan Reinauer 8483344802 Drop Kconfig.deprecated_options
Both remaining options, DRIVERS_PS2_KEYBOARD and ID_SECTION_OFFSET
are not likely to go away any time soon, so let's not keep them
in Kconfig.deprecated_options but move them close to the code they
control.

Change-Id: I310b877c5b3d5a3444056641c4aee07a48c4c4be
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1839
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16 01:13:40 +01:00
Stefan Reinauer fa2fc339c5 Drop Kconfig variable BOARD_HAS_HARD_RESET
hard_reset was indeed consolidated and moved into the southbridge
code a while ago, but the config variable was still kept alife, with
some duplicate code.

Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16 01:13:10 +01:00
Stefan Reinauer 5b635795cc SandyBridge/IvyBridge: Add IFD and ME firmware automatically
Right now coreboot's build process produces images that are
not booting on actual hardware because they are smaller than
the actual flash device and also don't have an IFD nor an ME
firmware in them. In order to produce bootable images, you
needed a wrapper script / extra step until now. With this
change, the resulting coreboot.rom is actually bootable.

Change-Id: I82714069fb004d4badc41698747a704bd9fed4da
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1771
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13 00:24:26 +01:00
Peter Stuge 9b48ef2733 Update SeaBIOS stable to the release-1.7.1 commit
Change-Id: I0dffe89c31e45914f795d9ad8efb787b5fdbb7a8
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/1583
Tested-by: build bot (Jenkins)
2012-10-16 03:31:05 +02:00
Alexandru Gagniuc 70c660fd14 pirq_routing: Allow routing with more than 4 PIRQ links
pirq_routing_irqs assumed that only four links are available for PIRQ
routing, INTA to INTD. Some chipsets provide more, up to INTH.
When pirq_routing_irqs found a link number greater than 4 in the pirq table,
it would not assign that IRQ. This is a shame, as it limits the flexibility
of routing IRQs.
Make the maximum number of links a Kconfig variable, and modify the code to
respect it. This works beatifully on the VX900, which provides 8 routable
interrupts.
While we're at it, also refactor pirq_routing_irqs, and add some much
needed comments.
Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this
function.
The copyrights added were determined from git log filename.

Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1482
Tested-by: build bot (Jenkins)
2012-10-04 04:27:29 +02:00
Kyösti Mälkki 651339bb5d Fix mptable build troubles
A missing mptable.c file got passed jenkins, got merged
and broke the build. Hopefully finally fix this.

Deletes unused files:
   src/mainboard/asus/dsbf/mptable.c
   src/mainboard/supermicro/x7db8/mptable.c

Change-Id: Ie81f5a6c4c69ab381f86a243bc8874395e69ee26
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1486
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-25 00:34:46 +02:00
Kyösti Mälkki 1c5071d175 Drop HAVE_MAINBOARD_RESOURCES
These existed to provide a hook to add reserved memory regions
in the coreboot memory table. Reserved memory are now
added as resources.

Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1414
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-08 03:44:51 +02:00
Denis 'GNUtoo' Carikli e4cece0d6f Add an option for Waiting for gdb connection if the gdb stub configuration is chosen.
Here's a quick demonstration on how to use it(tested on M4A785T-M).
  (gdb) file ./build/cbfs/fallback/coreboot_ram.debug
  Reading symbols from [...]/build/cbfs/fallback/coreboot_ram.debug...done.
  (gdb) set remotebaud 115200
  (gdb) target remote /dev/ttyUSB0
  Remote debugging using /dev/ttyUSB0
  _text () at src/arch/x86/lib/c_start.S:85
  85		call	hardwaremain

Change-Id: Ia49cbecc41deb061433bc39f5b81715da49edc98
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/1134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-23 07:50:07 +02:00
Steve Goodrich f026912776 Converted the FRAMEBUFFER_VESA_MODE to a choice.
Being a diligent soul, I changed the "enter a numeric value for the
mode you want" option to a choice of common modes.  New modes can be
added quite easily.

Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a
Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-on: http://review.coreboot.org/1036
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-24 21:54:08 +02:00
Stefan Reinauer 1c56d9b102 Add SPI flash driver
This driver is taken from u-boot and adapted to match
coreboot. It still contains some hacks and is ICH specific
at places.

Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/997
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10 23:52:44 +02:00
Stefan Reinauer fe4221848f Make CBFS output more consistent
- Prefix all CBFS output messages with CBFS:
- Add an option DEBUG_CBFS that is off by default. Without DEBUG_CBFS
  enabled, the code will no longer print all the files it walks for
  every file lookup.
- Add DEBUG() macro next to LOG() and ERROR() to specify which messages
  should only be visible with DEBUG_CBFS printed.
- Actually print a message when the file we're looking for was found. :)

old:
Searching for fallback/coreboot_ram
Check cmos_layout.bin
Check pci8086,0106.rom
Check fallback/romstage
Check fallback/coreboot_ram

Change-Id: I2d731fae17a5f6ca51d435cfb7a58d6e017efa24
Stage: loading fallback/coreboot_ram @ 0x100000 (540672 bytes), entry @ 0x100000
Stage: done loading.
new:
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (507904 bytes), entry @ 0x100000
CBFS: stage loaded.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/993
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-04 08:11:28 +02:00
Patrick Georgi 7e9b9d893c Add Kconfig options to handle the blobs repository
One option to allow using the repo (defaults to no),
one to let boards state that they require it in the
current configuration.

The build system checks out the repo if allowed, and
fails if the repo is requested by the configuration
but not desired by the user.

Change-Id: If71d80b329cf528aa467fcb0b4d9d7c7434aab27
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/957
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-05-01 00:09:27 +02:00
Uwe Hermann ad8c95f03b kconfig: Improve 'General setup' menu docs.
- Add documentation for COMPILER_GCC, and COMPILER_LLVM_CLANG.

 - SCANBUILD_ENABLE, CCACHE: Amend documentation.

 - SCANBUILD_REPORT_LOCATION: Document default dir, names of scan-build dirs.

 - INCLUDE_CONFIG_FILE: Add more verbose docs, show how to use it.

 - Fix typos/cosmetics/indentation, improve wording on some items.

Change-Id: I6b67b2c777868e4421405caaffe6631e69dddad2
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Reviewed-on: http://review.coreboot.org/893
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-17 10:56:16 +02:00
zbao f72237346d S3 code in coreboot public folder.
1. Move the Stack to high memory.
2. Restore the MTRR before Coreboot jump to the wakeup vector.

Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/623
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16 18:22:47 +02:00
Stefan Reinauer 8e073829ec Add support for Intel Panther Point PCH
Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/853
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04 19:10:51 +02:00
Stefan Reinauer dfb098d359 Add DEBUG_TPM option to Debugging menu
instead of having to edit the source code of tpm.c

Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/757
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30 17:56:22 +02:00
Stefan Reinauer 3008bbadcb Add TPM support to coreboot
and initialize the TPM on S3 resume

This patch integrates the TPM driver and runs TPM resume upon an ACPI S3
resume without including any other parts of vboot.

We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS
(that are incompatible with coreboot's) and it does a lot more than we
want it to do.

Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30 02:04:20 +02:00
Stefan Reinauer b89a761a63 Add Google ChromeOS vendorcode directory
... and hook it up in Kconfig. More code to come.

Change-Id: I24542d8ef97e2bce112c3aface681ceeb1a7c061
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/813
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30 01:59:38 +02:00
Vadim Bendebury 9202473d07 Add a config flag to enable time stamp collection
Add a new flag, make it dependent on EARLY_CBMEM_INIT

Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/712
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-28 20:43:36 +02:00
Vadim Bendebury e6b6aff28a Introduce config option to initialize CBMEM early.
We want to be able to communicate information between rom and ram
stages of coreboot. This configuration option will be used to
compile such ability in.

Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/710
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-28 20:28:05 +02:00
Rudolf Marek 6588802fa7 Disable the GDB stub by default
I would prefer to see the exception dump on serial rather than cryptic
GDB protocol.

Change-Id: Ib25513d33e6a31da24586fecb00adb5206bb43bd
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/811
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-03-26 16:06:21 +02:00
Stefan Reinauer aff6dc2149 Move SeaBIOS output out of coreboot source tree
Make sure SeaBIOS build files live under $(OUT) instead of
in the source tree.

Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/552
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-07 00:21:03 +01:00
Patrick Georgi a31bb0779a Unify ID_SECTION_OFFSET and mark it deprecated
We used to put the id section at -0x10, with some boards overriding
this to avoid collisions with romstraps.
Hardcode the location at -0x80, at the possible expense of some space
(0x70 bytes).
This also makes the section easier to find in a binary image.

At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
is moved to src/Kconfig.deprecated_options.

Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/549
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-01-18 11:21:39 +01:00
Stefan Reinauer c1efb90384 refactor vesa mode setting code and bootsplash code
- adds possibility to set a vesa mode without showing a bootsplash
- make bootsplash / mode setting code available in real mode.

Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/256
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:00:50 +02:00
Rudolf Marek 7f0e93060e Add support for the tracing infastructure in coreboot.
The compiler is forced to emmit special functions on every
entry/exit of the function. Add a compile time option
to support it. Function entries will be printed in
the console. The CONFIG_TRACE has more documentation.

Patch for userspace tools will follow.

Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/178
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:26:47 +02:00
Sven Schnelle 164bcfdd1b Add automatic SMBIOS table generation
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/152
Tested-by: build bot (Jenkins)
2011-08-26 20:08:52 +02:00
Cristian Măgherușan-Stanciu 9f52ea4c3c added a config option for ACPI debugging
Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/36
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-07-02 00:49:53 +02:00
Cristian Măgherușan-Stanciu d367b00c5b Add the coreboot config to CBFS
The CBFS will contain a new file, named 'config' of type 'raw' that is a
stripped-down version of the .config file that was used to build the
current coreboot image. For space savings, all the comments and empty
lines were removed from the original config, except for one that lists
the coreboot git revision that's built into the image.

This is done in order to easily reproduce the work of  someone else when
only having their ROM image. In theory the reproduce could even be
automated by a new dedicated make target.

This should work even with abuild now.

Change-Id: I784989aac0227d3679d30314b06dadaec402749e
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/46
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 06:43:23 +02:00
Sven Schnelle 8eee19d0ea Add option 'compress ramstage'
Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required for decompressing ramstage. This is probably
caused by the fact the decompression does a lot of single byte/word/qword
accesses, which are really slow on SPI buses. So give the user the option
to store ramstage uncompressed, if he has enough memory.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-02 19:53:04 +00:00
Stefan Reinauer 4885daadb3 Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.

This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>                                                                                                                                          



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-26 23:47:04 +00:00
Stefan Reinauer e50952f532 add FILO easy payload option
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 03:34:05 +00:00
Stefan Reinauer d85400d805 Handle drivers/ equally to any other sub directory.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 03:30:03 +00:00
Sven Schnelle 91321028ec Use subsystem id from devicetree.cb instead of Kconfig and move
all boards to the new config scheme.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 19:58:47 +00:00