Commit graph

7 commits

Author SHA1 Message Date
Duncan Laurie
211bb97c67 mb/google/eve: Update DPTF parameters
1) Set the critical temperature threshold to 100C to match changes
on other boards.  This is intended to reduce DPTF-initiated thermal
shutdowns before it has had a chance to react.

2) Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.

BUG=b:67459049
BRANCH=eve
TEST=manual performance/power testing on Eve hardware

Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-16 04:18:51 +00:00
Duncan Laurie
07a597feff mb/google/eve: Update thermal tuning parameters
Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.

BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.

Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-31 01:26:27 +02:00
Furquan Shaikh
231c198e2c mainboard/google/eve: Generate FPC device using SPI SSDT generator
Use the newly added SPI SSDT generator for adding FPC device.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully. Verified that the SSDT entry matches the
entry in mainboard.asl

Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18343
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:42:38 +01:00
Duncan Laurie
3c78eae369 google/eve: Adjust DPTF parameters
- Remove the 0mA entry for the charger performance table
- Slightly raise the passive limit for TSR2/TSR3 to 55C

BUG=chrome-os-partner:58666
TEST=manual testing on P1 system

Change-Id: I75c66afe04afbbdb64a45833eb938e57ff21b392
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18172
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-20 17:18:48 +01:00
Duncan Laurie
57dcf55538 google/eve: Add ASL code to describe SPI FPC1020 controller
There is ongoing work to link SPI bus and devices in to the devicetree
so this can be generated, but for now put in the raw ASL code to
describe this controller so it can be used by the factory.

BUG=chrome-os-partner:55538
TEST=successfully load fpc1020 kernel module on eve board

Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:23:38 +01:00
Martin Roth
d3d1f13599 mainboard & southbridge: Clear files that are just headers
These headers & comments indicating a lack of functionality don't help
anything.  We discourage copyrights and licenses on empty files, so
just clear these.

Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17657
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-05 19:20:49 +01:00
Duncan Laurie
81485d2763 google/eve: Add new board
Add the eve board files using kabylake and FSP 2.0.

BUG=chrome-os-partner:58666
TEST=build and boot on eve board

Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-11-01 22:54:25 +01:00