Commit Graph

10958 Commits

Author SHA1 Message Date
Patrick Georgi 77c9508f58 intel/fsp_bd82x6x: Fix cycle error some more
As a follow up to #6479 (63e1948643),
fix the remaining faulty loop.

Change-Id: I2c77efe620c71e939f4d74e48f90a166c782e5f5
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6569
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-10 05:28:48 +02:00
Patrick Georgi e887ca5a74 cbfstool: fix option parsing
"cbfstool create -B bootblock -s size" (in this order)
would break bootblock selection.

Change-Id: I9a9f5660827c8bf60dae81b519c6f026f3aaa0f3
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6564
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2014-08-09 19:54:09 +02:00
Edward O'Callaghan a0a019698d cpu/amd/geode_lx: Trivial - remove useless comment
Change-Id: I4b04f84fb2be7da4b7ffab71bb2c41142f455440
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6567
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-08-09 18:32:11 +02:00
Vladimir Serbinenko 1882527399 ivybridge: Don't propose to include systemagent on native boards.
Change-Id: Ib70a6741b55609840b6fd2fca16bcf9883bf143c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6566
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-08-09 18:19:53 +02:00
Vladimir Serbinenko 8a57b39223 lenovo/x201: Enable wake on LID and Fn key.
Change-Id: I485da5b8e9084c73f16b5df1c42879697fc0ac3d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6528
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-09 18:18:41 +02:00
Edward O'Callaghan 309a7ffc66 southbridge/amd/cs5536: Trivial style fix for trailing comment
Change-Id: Ia3a846497c220866e950a4b0bb53cb05c0e0cee2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6557
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-09 18:06:17 +02:00
Edward O'Callaghan cd2c1245f0 cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments
Lets try not to play games with the Lexer with fancy ASCII art. Doxygen
has a more well defined and useful syntax for annotations.

Change-Id: I6f6c58971f509064ae1e28a1740e50e2ae721513
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6550
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-09 18:06:09 +02:00
Edward O'Callaghan 728ff392e7 cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs
Change-Id: Ic65f8d2cbb5bc459cf513c6b34a5f1846cb2b897
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6549
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-09 18:04:32 +02:00
Stefan Reinauer ff0df2bba5 Exynos5420: clean up SPI driver
That extra struct is not needed, we already defined it earlier on.
Also fix coding style in the file.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I586d290f2f3ba2f44aca7fdee400b88547465599
Reviewed-on: https://chromium-review.googlesource.com/169780
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit f7df9f05fb707cac7976cd8a0b36bcf30cef8e0f)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6532
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-09 17:36:40 +02:00
Vadim Bendebury 2f6b0a9a4b Set check-lxdialog.sh mode properly
This script is used by 'make menuconfig', but being non executable it
fails to run, causing the make invocation failure.

Setting 'x' mode bits fixes the problem.

Change-Id: I925ca4ee056937b6c38ad34f5520fd621f9d9eb0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173564
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit 3ddb9d221ecc3df968853d765b566cf0648a7525)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6540
Tested-by: build bot (Jenkins)
2014-08-09 17:30:33 +02:00
Daniele Forsi 6ed2a242ee intel/eagleheights/Kconfig: Do not set twice MMCONF_BASE_ADDRESS
Remove the lines added in an apparently unrelated commit 53ad9f58 (Make CONFIG_HAVE_HIGH_TABLES consistent in where and how it is set.)
which touched the symbol HAVE_HIGH_TABLES in all files except this one and
keep those added the same day in commit 6842c029 (Remove MAINBOARD_OPTIONS, which is a relic from early kconfig development.)

Change-Id: Ib055c25a0a0795a50a36e65218c8f31e921f1502
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6417
Tested-by: build bot (Jenkins)
Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-09 17:29:44 +02:00
Edward O'Callaghan 4e9f5e3f36 superio/smsc/sio1036: Clean up RAMstage superio.c component
Remove spurious includes, unused variables and some wasted new lines.
Re-organise things to be consistent with other superio's.

Change-Id: I959bab2f7a83a1b9160d7f010a0de9638b30cf07
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6465
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-09 10:06:13 +02:00
Duncan Laurie c14e961f23 falco: Remove RTD2132 chip and setup from devicetree
This disables the spread spectrum clock and avoids errata.

Old-Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66673
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a7bf0d818c431221f4d014e3a0130bec8db7406e)

falco: Remove RTD2132 driver from kconfig

Original-Change-Id: I89ad9fbfbc58878602ed85ada918524426b5bc77
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66946
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 1d732eb5e4743546b8ed50c8c44965a687f61ab2)

Conflicts:
	src/mainboard/google/falco/Kconfig

Old-Change-Id: I317a0741779e272ad72b7272ef6f4a67abd66698
Reviewed-on: https://chromium-review.googlesource.com/167311
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit ffa6c89fbac04b4b6fceafd4ba97d39a285c4aa3)

Squashed two commits and corrected the subject line from 2312
to 2132.

Change-Id: If4f1e59999b70efe2de45522ba78051d9ed88dd7
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6527
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-08 20:00:08 +02:00
Furquan Shaikh 45f868d34f Falco/Slippy: remove unwanted scratchpad writes
Register range 0x4f000 - 0x4f08f includes scratchpad registers. Fastboot
works fine with these registers removed and graphics is initialized properly

Change-Id: Ic57c526a90619f4a073690440f6c5ac6ca96bf10
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65755
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7e7befdc3956cbc28d346545669cb55c566cf3ea)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6525
Tested-by: build bot (Jenkins)
2014-08-08 19:50:28 +02:00
Stefan Reinauer 42b1c34f7b ARMv7: Add stdint types needed for vboot library
Change-Id: I778ea787b20a7d7d7b202b1b5e7f956d2fde6629
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/169621
(cherry picked from commit 499a4802b5ad070a0b82f3b291073aa05fa7946e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6523
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-08 19:49:02 +02:00
Stefan Reinauer 9ad28b940f chromeos: Add code to read FMAP on ARM
On ARM the SPI flash is not memory mapped. Use the CBFS
interface to map the correct portion.

Change-Id: I8ea9aa0119e90a892bf777313fdc389c4739154e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/169781
Reviewed-by: David Hendrix <dhendrix@chromium.org>
(cherry picked from commit a263d3717e82c43fe91e7c4e82d167e74bf27527)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6522
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-08 19:29:51 +02:00
Stefan Reinauer da36bcf0d4 qemu-armv7/media.c: fix coding style
Change-Id: I01a11923fc1b250afeed36acc20793fd072421ba
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168574
Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 46b5f64096c55d0d9627cb9537fc4910e1bddcd9)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6520
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-08 18:32:28 +02:00
Duncan Laurie 9dd01eb416 falco: Add double function reset to ALC283 verb table
The ALC283 needs a double function reset to ensure that all settings
are reset and the firmware beep is functional.

Original-Change-Id: Id9ddc6f4914957f39c5f9cdfaaac354808929146
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@google.com>
(cherry picked from commit c59865ac464af308baedcd69aa662f46ff3a04d3)

Change-Id: Ie6f3a8179376bc97a6d22712dd965f5e0e6ec5d6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167313
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit b31d7a31b838e67a4b7f33119a3baea049d30a36)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6518
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2014-08-08 18:26:08 +02:00
Duncan Laurie 3bb40b93f8 chromeec: Implement full battery workaround at 6%
Currently the workaround for indicating a "full" battery kicks
in at 3%, but this turns out to be too high for some devices.
So move the workaround start point to 6% from full, or 94%.

Change-Id: Ib4305df3a68e89f3a10a096d0e89d8105ea9037b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 982dc496a0553c90dee56fda6411b7c21a5d7da9)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6521
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-08 18:11:52 +02:00
Ronald G. Minnich 5b10fc5242 Pit: remove backlight delay
Change-Id: Ia2e5427fec1bfff9babb9c59a3878323277f4f4c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66555
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 2b96235123d55db3ff5ae5c2454b65de831a1c18)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6524
Tested-by: build bot (Jenkins)
2014-08-08 18:11:15 +02:00
Julius Werner 45d2ff317c exynos5420: Implement support to boot with USB A-A firmware upload
This patch ports the USB A-A firmware upload functionality from
exynos5250 over to exynos5420. Essentially just like a conflictless
cherry-pick of 9e69421f5f0eebf88c09913dee90082feab2856c. It also fixes
the exact same bug with SPI initialization for Pit and Kirby.

Old-Change-Id: Ief0ed54c0beb2701e51201041f9bc426b2167747
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65751
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 5dff43f929478f83939221df13b961a69f89b132)

exynos5: Fix trivial style nits

A few curly braces on the wrong line.

Old-Change-Id: I4ddac4476c6509dc1716e8c1915fbdb67d346786
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66153
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 41e3fd9eaafe36433723f4e96a6d94c04e5fbafb)

Squashed two related commits.

Change-Id: I22d579693b5e7270aacb45bbe3557e40893dd1f8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6500
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-08 17:41:46 +02:00
Vladimir Serbinenko 782ac36cfa lenovo/x230: Enable wake on LID and Fn key.
Change-Id: Ifc7208400b0bdfa2b9b70773bd24e9f9df7f8048
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6526
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-08 07:39:55 +02:00
Edward O'Callaghan 91810ddf79 device/oprom/realmode: Sanitize header inclusion
Alphabetise includes to avoid duplication.

Change-Id: I7fa6998cd736bad2bab4a6b1a65d48a21d6220d9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6415
Tested-by: build bot (Jenkins)
Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com>
2014-08-08 03:32:13 +02:00
Ronald G. Minnich 62997e0981 ARMV7: threading support for cooperative multitasking
These functions add support for cooperative multitasking.
Currently, since we only have one ARM SOC that uses or supports multitasking,
arch_get_thread_stackbase returns CONFIG_STACK_BOTTOM for the thread stack.
We may end up having to make a cpu-specific function that arch_get_thread_stackbase calls,
but let's avoid adding complexity until we're sure we need to. We also wish to avoid
creating Yet Another Config Variable but will do so if pressed.

The switch code only saves r4-r11 and lr, which is consistent with the standard.

Change-Id: I0338a9c11127351e1f3a190bc51a7a558420b141
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66845
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 22b62af3c26b6b504498b434d29a56a8932f3061)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6517
Tested-by: build bot (Jenkins)
2014-08-08 00:10:17 +02:00
David Hendricks ad4afe9b04 armv7: Fix dcache writethrough policy handling
The "bufferable" bit was erroneously set for the writethrough policy
making it the same as writeback.

(credit to jwerner for pointing this out)
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I567d57f0e522cb4b82988894ba9b4638642bf8db
Reviewed-on: https://chromium-review.googlesource.com/167323
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Tested-by: ron minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 36cf13839604c349692865475f3011afd08965b4)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6515
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07 23:55:56 +02:00
Ronald G. Minnich 71e1c8303b Exynos 5420: skip the EDID read if there is already an EDID.
For many boards, the EDID is known and is set in the ramstage. Reading
the EDID is slow and if we have it we do not want to reread it.

If the raw_edid struct member is non-null, skip reading the EDID.

Change-Id: I63fb11aa90b2f739a351cdc3209faac2713ea451
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/167116
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: ron minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@google.com>
(cherry picked from commit 80f48655570de544a7e1939c4f5f28713f11d829)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6514
Tested-by: build bot (Jenkins)
2014-08-07 23:55:37 +02:00
Ronald G. Minnich 34352d16a9 Possible thread stack implementation.
Architecture provides a function for thread stack base, thread code uses it.
Build and boot tested on Falco with multitasking on and off.

Change-Id: I5016fab47f9954379acf7702ac7965b0a70c88ed
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66578
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 3c6afef30c1a0ad6fba0fb76acc792184d924247)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6513
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07 23:55:15 +02:00
David Hendricks 0ffa11bdbb exynos5420: Set the CLK_DIV_CPERI1 value as per manual
Set the CLK_DIV_CPERI1 value as recommended by the
0.02 UM section 7.9.1.25.
This suggests to use 0x3F3F0000 as the value to be
set to save power.

This is ported from https://gerrit.chromium.org/gerrit/#/c/64905
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I89a6a72d20374a513019a272628a05e139b31773
Reviewed-on: https://gerrit.chromium.org/gerrit/66787
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 34be13b008e262c641268b7c1c6a08e49f18fc37)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6512
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-07 23:54:54 +02:00
Gabe Black ee4bfbf3e1 exynos: Set up caching in the bootblock.
This improves firmware boot time substantially. Because cbmem isn't available
yet, we need to allocate some space in sram for the ttb. Doing cache
initialization in the bootblock means we can implement this once per CPU
instead of once per mainboard.

Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65938
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73)

exynos5420: flush caches and disable MMU in resume path

This patch flushes the caches and disables the MMU before resuming.

c32b9b3 ("Set up caching in the bootblock.") had a bug where the
dcache and MMU remained enabled in the resume path. This caused
the machine to hang on resume. However, other bugs were preventing
us from testing this properly earlier on so it went unnoticed until
now.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e
Reviewed-on: https://chromium-review.googlesource.com/67007
Reviewed-by: ron minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d)

Squashed two related commits.

Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6511
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07 23:05:10 +02:00
Ronald G. Minnich e10ef42a55 Exynos5420: invoke the cooperative threading in udelay
Call thread_yield_microseconds in udelay. This works with and without
COOP_MULTITASKING enabled.

Change-Id: Ib3eab00d1630dc4daada850e7458ab89702d1864
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66327
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 12e55ba8a68e5d40e08ad169848bdf274887ce0b)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6510
Tested-by: build bot (Jenkins)
2014-08-07 23:04:28 +02:00
Aaron Durbin ca63027ef7 cbfstool: process cbfs_payload_segment(s) in host byte order
The printing routines of the cbfs_payload_segment assumed the type
could be accessed in host order. Each of the fields need to be
converted to the host order before inspecting the fields. In addition,
this removes all the ntoh*() calls while processing the
cbfs_payload_segment structures.

cbfstool would crash adding entries or just printing entries
containing a payload when -v was passed on the command line.

Change-Id: Iff41c64a99001b9e3920e2e26828c5fd6e671239
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6498
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-08-07 19:05:43 +02:00
Marc Jones 4acd8ea778 slippy/flaco/peppy: setup beep verbs
Add verb setting for beep during recovery and dev mode.
Requires depthcharge CL.

Change-Id: I13cbb4e889ebc4c27bb4ab9fa49601b03e872d09
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66519
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit c072543946b317192a8e80a744c1515deb414456)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6502
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06 23:44:00 +02:00
Stefan Reinauer 61fcd14561 Exynos5: Remove unneeded USB delays
Change-Id: I1144e9d6d6c4278842fdd36743c8a88555f81707
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65912
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 95b518877edc88347ce9725ffee32f3aed0de7dc)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-06 23:09:46 +02:00
Ronald G. Minnich bc6cc112e2 Exynos5420: tighten up display port delays
Shorten a few delays, and make some delays shorter but let the
loops have a higher termination count (i.e. give it the same
amount of time to warm up, but check more frequently).

Change-Id: Id9fe846ae3a8d792b14d62aea4e98d8aad05be43
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66156
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit a112e77f2f21f41f982ca22bebdac213cc8d233a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6506
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06 23:09:32 +02:00
Hung-Te Lin f2c4241b81 exynos5420: Fix mmc clock source.
The DWMMC controller internally divided clock by values in CLKSEL registers,
so we must adjust MMC clock for that.

Change-Id: I44f55b634cfc6fd81d76631595b6928c862a219f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66657
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 89ed6c9154f16c6b8d01af03c0b78914773eb469)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6504
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06 23:09:02 +02:00
Ronald G. Minnich d6b16f54b9 Set armv7 up for cpu_info to work as on x86 (so threads can work)
On x86, cpu_info lives at the top of stack. Make the arm do that as
well, as the threading model needs that and so will multicore support.

As part of this change, make the stack size a power of 2.
Also make it much smaller -- 2048 bytes is PLENTY for ram stage.

Note that the small stack size is counterintuitive for rom stage.  How
can this work in rom stage, which needs a HUGE stack for lzma? The
main use of STACK_SIZE has always been in ram stage; since 2002 or so
it was to size per-core stacks (see, e.g.,

src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE

and, more recently, thread stacks. So, we define the STACK_TOP for rom
and ram stage, but the STACK_SIZE has no real effect on the ROM stage
(no hardware red zones on the stack) and hence we're ok with actually
defining the "wrong" stack size. In fact, the coreboot_ram ldscript
for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from
CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc

Observed stack usage in ramstage:
BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1
Jumping to boot code at 23104044
CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes
entry    = 23104044

Which means we do need 2K, not 1K.

Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66135
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6501
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-06 22:07:06 +02:00
Vladimir Serbinenko 7111835f39 lenovo/x201: Enable pcie lanes in wwan slot.
Change-Id: I7332eeed244877252074e661f1c256a69a9b428a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6482
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-06 20:51:48 +02:00
Edward O'Callaghan 1c07c2205e mainboard/amd: De-ASCIIartify AGESA board headers
As was done for the reference boards in:

cd30951 mainboard/amd: De-ASCIIartify reference boards

Change-Id: Ie34aa5269388b771daa6934f8aff0314ac6778d5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6290
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-08-06 15:36:12 +02:00
Dave Frodin 70d4b5261e gizmosphere/gizmo: Change the PCIe GPP to two x1 ports
Gizmo sends two southbridge GPP PCIe lanes to its high speed
edge connector. This change will allow developers to create
two x1 slots on an extender card.

Change-Id: Iba6c1a4caf7846d12e3960775d7bc906ca8ff385
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6499
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-06 15:06:17 +02:00
Edward O'Callaghan 5103cc3d53 lenovo/t530/mainboard.c: Include header `h8.h` for prototype
Change-Id: I05cea020e77051bd3bc0e93b0c70e12b9b985d05
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6398
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-06 01:11:54 +02:00
Gabe Black 396b072297 tegra124: Add a stub implementation of the tegra124 SOC.
Most things still needs to be filled in, but this will allow us to build
boards which use this SOC.

Change-Id: Ic790685a78193ccb223f4d9355bd3db57812af39
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170836
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 462456fd00164c10c80eff72240226a04445fe60)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6431
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-05 18:44:53 +02:00
Gabe Black 1ee2c6dbdf libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig.
When libpayload header files are included in the payload itself, it's possible
that the payloads config settings will conflict with the ones in libpayload.
It's also possible for the libpayload config settings to conflict with the
payloads. To avoid that, the libpayload config settings have _LP_ (for
libpayload) added to them. The symbols themselves as defined in the Config.in files
are still the same, but the prefix added to them is now CONFIG_LP_ instead of just
CONFIG_.

Change-Id: Ib8a46d202e7880afdeac7924d69a949bfbcc5f97
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65303
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 23e866da20862cace0ed2a67d6fb74056bc9ea9a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6427
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-08-05 18:44:08 +02:00
David Hendricks b77431336e exynos5420: get rid of old exynos5420_config_l2_cache()
We set up L2 cache early in romstage now so the old
function is now redundant.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef
Reviewed-on: https://gerrit.chromium.org/gerrit/65428
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f)

exynos: stack size: Increase the stack size to 16KB.

The lzma decoding function in the RAM stage allocates nearly 16KB on the stack
which is shared between the bootblock, rom stage, and ram stage. The stack had
been much too small and needed to be expanded.

Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65937
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b)

exynos: gpio: add a bigger delay when reading board strappings

Z-state pins were not reading reliably with a 5us delay, so increase
it to 15us.

This is ported from https://gerrit.chromium.org/gerrit/64338

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35
Reviewed-on: https://gerrit.chromium.org/gerrit/65727
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084)

exynos5420: enable DMC internal clock gating

lets enable memory controller internal clock gating for ddr3.
with these bits enabled we save some power out of ddr3.

This is ported from https://gerrit.chromium.org/gerrit/#/c/60774

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f
Reviewed-on: https://gerrit.chromium.org/gerrit/65728
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781)

exynos5420: Correct the 600MHz PMS value

In UM ver0.02, 600MHz clock PMS values differs from what is programed
currently. Though this also results in 600MHz clock, but it is better to
match what UM says. This patch chnage this as per UM

This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3
(Note: we already used the correct 600MHz value for KPLL)

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5
Reviewed-on: https://gerrit.chromium.org/gerrit/65726
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f)

Squashed five commits pertaining to  exynos.

Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6425
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-05 18:43:42 +02:00
Edward O'Callaghan 18fe07ed22 northbridge/via/vx800: Fix out-of-bounds read due to off-by-one
Change-Id: Ia7fda59b60b2148dd4d246686bd94d2334b23eb5
Found-by: Coverity Scan
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6485
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-05 02:12:20 +02:00
Elyes HAOUAS 68a97164d3 lenovo/t520/mainboard.c: Include header `h8.h` for prototype
Change-Id: I5ac6608ebf78f2d48bc7f68bce9eae7a2be82332
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6424
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04 21:44:50 +02:00
Shawn Nematbakhsh 650b00c1bf peppy: Force enable ASPM on PCIe Root Port 1
(Clone of Falco change Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8)

Old-Change-Id: I5feba8fdbafba6d2de9f7d3de6170defc0d45a32
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66536
Reviewed-by: Dave Parker <dparker@chromium.org>
(cherry picked from commit b78a872a6647d7bb82f6c06a75e4075e451a1622)

peppy: Disable unused clocks

CLKOUT for PCIE ports 2-5 and CLKOUT_XDP are not used
and can be disabled.

This change was modled after the change made in Falco:
Falco-Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b

The only difference per schematic for Peppy was PCIe 1 supports
a NGFF interface. PCIe 0 is connected to WLAN.

Old-Change-Id: Ib4871cb2655316cb260ab33ada6b9d81f271377f
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66693
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 8f12335013a510dee3c21b55251ab00c0fbac609)

Squashed two related commits.

Change-Id: Ibc5b902018eec07fdccaa8c6cb066ce918f6a6b5
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6419
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04 21:43:36 +02:00
Patrick Georgi 6fa6843a8d sconfig: improve argument parsing
Running sconfig with four arguments where the third
does not match /-./ made sconfig use uninitialized
memory to build the output filename.

Change-Id: If4a147ff23771ca9b6a913605af60249be1ca3d0
Found-By: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6483
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04 20:57:12 +02:00
Paul Menzel 80fd01d2cc util/sconfig/main.c: Remove assigned but unused variable `link`
Cppcheck 1.65 report the style style issue below.

	[main.c:434]: (style) Variable 'link' is assigned a value that is never used.

So remove the variable `link` as it is not needed.

Change-Id: Ib77b80b74a70985a76eaa3247c4a43832ef23a59
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6488
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04 20:57:10 +02:00
Edward O'Callaghan 2b48b65b19 northbridge/intel: Out of bounds write to array in gma.h
The signature[] array in the mailbox struct opregion_header_t has
IGD_OPREGION_SIGNATURE written to it with a
sizeof(IGD_OPREGION_SIGNATURE) and not a sizeof(signature[]). This
resulted in a silent off-by-one out of bounds illegal write.

Change-Id: I651620a753c743dd2ed2af51c012c27c14a5ea25
Found-by: Coverity Scan
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6473
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-04 14:01:52 +02:00
Edward O'Callaghan 5cfef13f8d cpu/intel: Fix out-of-bounds read due to off-by-one in condition
If power_limit_1_time > 129 is false then power_limit_1_time can have a
value of up to 129 leading to an out-of-bounds illegal read indexing the
power_limit_time_sec_to_msr[] array. Thankfully all call sites have been
doing the right thing up until now so the issue has not been visible.

Change-Id: Ic029d1af7fe43ca7da271043c2b08fe3088714af
Found-by: Coverity Scan
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6478
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-04 13:58:14 +02:00