Commit graph

7 commits

Author SHA1 Message Date
Kyösti Mälkki
fee73df07a Auto-declare chip_operations
The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-22 05:06:41 +02:00
Kerry Sheh
91be49b2d0 SIO: condition compile Nuvoton WPCM450 early_init.c
Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450

Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/566
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-02-05 17:45:08 +01:00
Stefan Reinauer
5ff7c13e85 remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01 19:07:45 +01:00
Alexandru Gagniuc
1a2b318625 Do not compile nuvoton superio for all board
The nuvoton WPCM450 code is compiled for all boards regardless of
whether or not they use it. Compile it only for boards needing it.

Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/129
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-09 20:11:01 +02:00
efdesign98
00c8c4a316 Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes.  The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements.  This particular change
affects all mainboards that use the SB700, and their changes are
include herein.  These mainboards are:
  Advansus a785e,
  AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
  Asrock 939a785gmh,
  Asus m4a78-em, m4a785-m,
  Gigabyte ma785gm,
  Iei Kino-780am2-fam10
  Jetway pa78vm5
  Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.

Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 00:20:59 +02:00
Stefan Reinauer
13508b94cb Drop baud rate init to an arbitrary baud rate from Super I/O code.
See discussion at                                                                                                                                                               
http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html                                                                                                                 
                                                                                                                                                                                
config->com1, devicetree.cb cleanup and init_uart8250() removal                                                                                                                 
will follow once this patch is comitted                                                                                                                                         
                                                                                                                                                                                
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>                                                                                                                   
Acked-by: Patrick Georgi <patrick@georgi-clan.de>                                                                                                                               

Updated to drop com1, com2.... from config structure and devicetree.cb



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 21:33:40 +00:00
Zheng Bao
8a281880a3 This is for board Supermicro H8scm. The code was done by existing chips and
superiotool.

WPCM450 is more like an EC. SuperIO is just a part of multi-features.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27 16:33:09 +00:00