Angel Pons 8120759d90 Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake ... According to a comment on fa1a07b, the 100MHz clock is the Ivy Bridge only clock, not the 133MHz one. Change-Id: I28fed4a9264b96f93b9e88325f547a5db512514c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28377 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-08-30 14:47:41 +00:00
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index.md	Documentation: Add SandyBridge NRI feature matrix	2018-06-15 09:15:20 +00:00
nri.md	Documentation/northbridge/intel/sandybridge/*: fix typos	2018-08-22 07:03:13 +00:00
nri_features.md	Documentation: Add SandyBridge NRI feature matrix	2018-06-15 09:15:20 +00:00
nri_freq.md	Documentation/northbridge/intel/sandybridge/*: fix typos	2018-08-22 07:03:13 +00:00
nri_read.md	Documentation/northbridge/intel/sandybridge/*: fix typos	2018-08-22 07:03:13 +00:00
nri_registers.md	Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake	2018-08-30 14:47:41 +00:00
timA_lane0-3_adjust_fine.png	Documentation: Update index.md and move files	2018-05-30 09:14:48 +00:00
timA_lane0-3_discover_420x.png	Documentation: Update index.md and move files	2018-05-30 09:14:48 +00:00
timA_lane0-3_rt53.png	Documentation: Update index.md and move files	2018-05-30 09:14:48 +00:00
timA_lane0-3_rt54.png	Documentation: Update index.md and move files	2018-05-30 09:14:48 +00:00
timA_lane0-3_rt55.png	Documentation: Update index.md and move files	2018-05-30 09:14:48 +00:00