68 lines
2.3 KiB
Markdown
68 lines
2.3 KiB
Markdown
# x86 architecture documentation
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This section contains documentation about coreboot on x86 architecture.
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* [x86 PAE support](pae.md)
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## State of x86_64 support
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At the moment there's only experimental x86_64 support.
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The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support
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*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*.
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In order to add support for x86_64 the following assumptions were made:
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* The CPU supports long mode
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* All memory returned by malloc must be below 4GiB in physical memory
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* All code that is to be run must be below 4GiB in physical memory
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* The high dword of pointers is always zero
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* The reference implementation is qemu
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* The CPU supports 1GiB hugepages
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* x86 payloads are loaded below 4GiB in physical memory and are jumped
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to in *protected mode*
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## Assuptions for all stages using the reference implementation
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* 0-4GiB are identity mapped using 2MiB-pages as WB
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* Memory above 4GiB isn't accessible
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* page tables reside in memory mapped ROM
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* A stage can install new page tables in RAM
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## Page tables
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Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes
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the page tables to a file which is then included into the CBFS as file called
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`pagetables`.
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To generate the static page tables it must know the physical address where to
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place the file.
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The page tables contains the following structure:
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* PML4E pointing to PDPE
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* PDPE with *$n* entries each pointing to PDE
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* *$n* PDEs with 512 entries each
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At the moment *$n* is 4, which results in identity mapping the lower 4 GiB.
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## Basic x86_64 support
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Basic support for x86_64 has been implemented for QEMU mainboard target.
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## Reference implementation
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The reference implementation is
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* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md)
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* [QEMU Q35](../../mainboard/emulation/qemu-q35.md)
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## TODO
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* Identity map memory above 4GiB in ramstage
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## Future work
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1. Fine grained page tables for SMM:
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* Must not have execute and write permissions for the same page.
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* Must allow only that TSEG pages can be marked executable
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* Must reside in SMRAM
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2. Support 64bit PCI BARs above 4GiB
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3. Place and run code above 4GiB
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## Porting other boards
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* Fix compilation errors
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* Test how well CAR works with x86_64 and paging
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* Improve mode switches
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* Test libgfxinit / VGA Option ROMs / FSP
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