Raul E Rangel 0318dc169e soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10ms ... The ChromeEC might take longer than 1ms for the peripheral channel to be enabled. The PLTRST# interrupt handler takes about ~539us. This doesn't account for the time it takes for the interrupt handler to be scheduled. Increasing the timeout to 10ms gives ample time. BUG=b:188188172, b:188935533 TEST=Boot guybrush and no longer see channel enable errors Suggested-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-05-25 15:20:27 +00:00
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cezanne	soc/amd: reduce MCACHE size with psp_verstage	2021-05-22 05:47:23 +00:00
common	soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10ms	2021-05-25 15:20:27 +00:00
picasso	soc/amd: reduce MCACHE size with psp_verstage	2021-05-22 05:47:23 +00:00
stoneyridge	soc/amd: factor out ACPI ALIB function numbers to common code	2021-05-08 17:56:10 +00:00
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