coreboot-kgpe-d16/src/mainboard/google/fizz
Shelley Chen 031c818633 google/fizz: Configure memory
Read DRAM SPD and populate MemorySpdPtr fields
in UPD data structure for FSP.

BUG=b:36490168, b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a
     We are currently working on bringup and have no
     hardware to test on yet.

Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-24 19:17:47 +02:00
..
acpi
acpi_tables.c
board_info.txt
boardid.c
bootblock.c
chromeos.c vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by default 2017-03-28 22:15:46 +02:00
chromeos.fmd
devicetree.cb soc/intel/skylake: Split AC/DC settings for Deep Sx config 2017-04-13 09:09:16 +02:00
dsdt.asl
ec.c
ec.h
gpio.h google/fizz: Transfer gpio from schematic 2017-03-23 21:09:40 +01:00
Kconfig google/fizz: Configure memory 2017-04-24 19:17:47 +02:00
Kconfig.name
mainboard.c
Makefile.inc
ramstage.c
romstage.c google/fizz: Configure memory 2017-04-24 19:17:47 +02:00
smihandler.c