5dd76fd4cc
Change-Id: Iad5540e791075270453a136a058823c28647f93a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <assert.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/systemagent.h>
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/* Returns base of requested region encoded in the system agent. */
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static inline uintptr_t system_agent_region_base(size_t reg)
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{
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#if defined(__SIMPLE_DEVICE__)
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pci_devfn_t dev = SA_DEV_ROOT;
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#else
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struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
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#endif
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/* All regions concerned for have 1 MiB alignment. */
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return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);
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}
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static inline uintptr_t smm_region_start(void)
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{
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return system_agent_region_base(TSEGMB);
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}
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static inline size_t smm_region_size(void)
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{
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return system_agent_region_base(TOLUD) - smm_region_start();
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = smm_region_start();
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*size = smm_region_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/*
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* We need to make sure ramstage will be run cached. At this point exact
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* location of ramstage in cbmem is not known. Instruct postcar to cache
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* 16 megs under cbmem top which is a safe bet to cover ramstage.
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*/
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
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MTRR_TYPE_WRBACK);
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/* Cache the TSEG region */
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postcar_enable_tseg_cache(pcf);
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}
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