coreboot-kgpe-d16/src/soc/imgtec/pistachio
Ionela Voinescu b9d961550c urara: add support for DMA coherent memory area
The information about the DMA memory area is further passed
through the coreboot table to the payload.

BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA; DMA memory area was used to test the
     functionality of the DWC2 USB controller driver; behavior was
     as expected.
BRANCH=none

Change-Id: I658e32352bd5fab493ffe15ad9340e19d02fd133
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0debc105b072a37e2a8ae4098a9634d841191d0a
Original-Change-Id: Icf69835dc6a385a59d30092be4ac69bc80245336
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/235910
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9593
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13 12:19:38 +02:00
..
include/soc urara: add support for DMA coherent memory area 2015-04-13 12:19:38 +02:00
bootblock.c pistachio: implement timer support 2015-04-09 00:29:09 +02:00
cbmem.c pistachio: set correct CBMEM top address 2015-04-09 02:30:53 +02:00
Kconfig pistachio: allow more room for bootblock 2015-04-09 00:29:46 +02:00
Makefile.inc pistachio: add SOC descriptor 2015-04-09 02:32:31 +02:00
monotonic_timer.c pistachio: add timer frequency for SOC; correct platform ID 2015-04-09 02:32:59 +02:00
romstage.c pistachio: don't open code ramstage loading 2015-03-28 17:43:47 +01:00
soc.c pistachio: add SOC descriptor 2015-04-09 02:32:31 +02:00
spi.c pistachio: Change all SoC headers to <soc/headername.h> system 2015-04-07 19:38:03 +02:00
uart.c imgtec/pistachio: Bring uart driver to modern standards 2015-03-30 20:41:22 +02:00