420b0f692b
Corrected platform ID and added timer frequency for SOC. The timer frequency is half the CPU frequency. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: If7e03232106b52f2522fc7da586bdaf95f5eefec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d94789950d5300bbe5defbf529480d8d545e743e Original-Change-Id: I1187e4b5280eaf796777d882a2e154e2808e9e37 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241426 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9193 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <timer.h>
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#include <timestamp.h>
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#include <arch/cpu.h>
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#include <soc/cpu.h>
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#define PISTACHIO_CLOCK_SWITCH 0xB8144200
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#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
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static int get_count_mhz_freq(void)
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{
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static unsigned count_mhz_freq;
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if (!count_mhz_freq) {
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if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
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count_mhz_freq = 25; /* FPGA board */
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else {
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/* If MIPS PLL external bypass bit is set, it means
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* that the MIPS PLL is already set up to work at a
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* frequency of 550 MHz; otherwise, the crystal is
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* used with a frequency of 52 MHz
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*/
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if (read32(PISTACHIO_CLOCK_SWITCH) &
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MIPS_EXTERN_PLL_BYPASS_MASK)
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/* Half MIPS PLL freq. */
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count_mhz_freq = 275;
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else
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/* Half Xtal freq. */
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count_mhz_freq = 26;
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}
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}
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return count_mhz_freq;
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}
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void timer_monotonic_get(struct mono_time *mt)
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{
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mt->microseconds = (long)timestamp_get();
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}
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uint64_t timestamp_get(void)
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{
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return read_c0_count()/get_count_mhz_freq();
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}
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