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Iru Cai 03e96a8a9e mainboard/hp: Add HP Elitebook 2760p
The code is generated by autoport.

The flash chip is socketed beside the WLAN slot. The EHCI debug port
is on right side of the laptop beside the RJ11 connector.

Things that work:
- memory: 0+8G, 4G+8G
- Linux (Linux Mint 18.1 with Linux 4.4)
- native graphics init + SeaBIOS payload with SeaVGABIOS
- all 3 USB ports
- WLAN
- WWAN
- SD card reader
- expresscard
- S3 suspend and resume
- internal flashing after IFD is unlocked and coreboot is flashed
- keyboard, trackpoint and touchpad
- fan control
- AC and battery status

Issues:
- Wacom digitizer does not work (even after I add it in DSDT)
- GRUB payload will freeze (in all Elitebooks, including chainloading GRUB
  from SeaBIOS)

Things that are not tested:
- smart card reader
- cable modem

(EC) blobs:

This laptop uses SMSC KBC1126-NU as EC. It needs two blobs in the
flash chip. You can use the tools in util/kbc1126 to extract them
from OEM firmware, and use the following configuration to insert
them to coreboot image:

  -> Chipset
    -> Add firmware images for KBC1126 firmware

Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-18 15:30:35 +00:00
3rdparty Update vboot submodule to upstream master 2017-07-31 20:30:55 +00:00
configs configs: Add intel/galileo test configurations 2017-06-20 18:10:47 +02:00
Documentation Documentation: Add binary extraction documentation 2017-08-10 20:11:16 +00:00
payloads payload/tianocore: Add patch to preserve coreboot table 2017-08-18 15:23:53 +00:00
src mainboard/hp: Add HP Elitebook 2760p 2017-08-18 15:30:35 +00:00
util util/lint: Change final-newlines to lint-test from lint-extended-test 2017-08-17 11:27:02 +00:00
.checkpatch.conf Fix files with multiple newlines at the end. 2017-07-24 15:08:08 +00:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore copy & update test routines from what-jenkins-does 2017-08-11 15:24:56 +00:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
MAINTAINERS MAINTAINERS: Update support list 2017-07-15 21:53:21 +00:00
Makefile copy & update test routines from what-jenkins-does 2017-08-11 15:24:56 +00:00
Makefile.inc Fine-tune compiler flags 2017-08-11 15:56:12 +00:00
README README: Update requirements 2017-06-27 17:04:32 +00:00
toolchain.inc toolchain.inc: Use -Wstack-usage only on gcc 2017-06-19 22:17:01 +02:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * https://www.coreboot.org/Supported_Motherboards
 * https://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)
 * pkg-config
 * libssl-dev (openssl)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult https://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  https://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.