Ravi Kumar Bokka 65af8bbe72 soc/qualcomm/sc7280: DDR One-Time-Training Support ... Introduce DDR One-Time-Training Support Device reboots without training from second iteration and also DDR training data is 32kb size, hence update required in memlayout and to sync with upstream changes the Fmap size even got bumped up. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>		2021-09-03 16:58:32 +00:00
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board.h	herobrine: get boardid from GPIO configuration	2021-07-23 17:21:07 +00:00
board_info.txt
boardid.c	herobrine: get boardid from GPIO configuration	2021-07-23 17:21:07 +00:00
bootblock.c
chromeos.c	mainboard/google/herobrine: Add configuration for SD card detect pin	2021-07-22 06:39:32 +00:00
chromeos.fmd	soc/qualcomm/sc7280: DDR One-Time-Training Support	2021-09-03 16:58:32 +00:00
devicetree.cb
Kconfig	mb/*: Specify type of MAINBOARD_PART_NUMBER once	2021-07-26 14:05:29 +00:00
Kconfig.name	mb/google/herobrine: Add Senor and Piglin variants	2021-06-29 16:37:35 +00:00
mainboard.c	mainboard/google/herobrine: Configure SDCC clock	2021-09-03 16:53:56 +00:00
Makefile.inc	mb/google/herobrine: Retrieve SKU ID from EC	2021-07-21 16:21:01 +00:00
reset.c
romstage.c