Kyösti Mälkki 05d6ffba0f Intel cpus: improve CPU compatibility of new CAR ... Most or many Xeons have no MSR 0x11e. I have previously tested that a HT-enabled P4 (model f25) can execute this but will not have cache-as-ram enabled. Should work for non-HT P4. Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/644 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2012-03-31 11:58:51 +02:00
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amd	Rename AMD_AGESA to CPU_AMD_AGESA	2012-03-16 22:40:35 +01:00
intel	Intel cpus: improve CPU compatibility of new CAR	2012-03-31 11:58:51 +02:00
via	Via Epia-N and C3: Set ioapic delivery type in Kconfig	2012-03-16 20:40:47 +01:00
x86	Make MTRR min hole alignment 64MB	2012-03-30 17:56:10 +02:00
Kconfig	Add support for RAM-less multi-processor init	2012-03-31 11:57:47 +02:00
Makefile.inc	qemu: drop "northbridge.c" from src/cpu/...	2010-03-29 21:17:25 +00:00