coreboot-kgpe-d16/src/devices
Gabe Black fb8632ab58 oprom: Ensure that mode information is valid before putting it in the tables.
At least when CONFIG_CHROMEOS is turned on, it's possible for
CONFIG_FRAMEBUFFER_KEEP_VESA_MODE to be set but for there not to be any valid
information to put into the framebuffer coreboot table. That means that what's
put in there is junk, probably all zeroes from the uninitialized global
variable the mode information is stored in (mode_info).

When a payload uses libpayload and turns on the coreboot framebuffer console,
that console will attempt to scroll at some point and decrease the cursor's y
coordinate until it is less than the number of rows claimed by the console.
The number of rows is computed by taking the vertical resolution of the
framebuffer and dividing it by the height of the font. Because the mode
information was all zeroes, the coreboot table info is all zeroes, and that
means that the number of rows the console claims is zero. You can't get the
unsigned y coordinate of the cursor to be less than zero, so libpayload gets
stuck in an infinite loop.

The solution this change implements is to add a new function,
vbe_mode_info_valid, which simply returns whether or not mode_info has anything
in it. If not, the framebuffer coreboot table is not created, and libpayload
doesn't get stuck.

Change-Id: I08f3ec628e4453f0cfe9e15c4d8dfd40327f91c9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/1758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 04:22:34 +01:00
..
oprom oprom: Ensure that mode information is valid before putting it in the tables. 2012-11-12 04:22:34 +01:00
agp_device.c Various cosmetic and coding style fixes in src/devices. 2010-11-04 23:23:47 +00:00
cardbus_device.c Various cosmetic and coding style fixes in src/devices. 2010-11-04 23:23:47 +00:00
cpu_device.c AMD northbridges: factor out CPU allocation 2012-08-27 15:36:47 +02:00
device.c Revert order in VGA device choice 2012-10-07 07:24:58 +02:00
device_romstage.c Make the device tree available in the rom stage 2012-08-04 18:05:39 +02:00
device_util.c Add name field for device 2012-11-06 00:23:54 +01:00
dummy_chip_ops.c Every chip must have chip_operations 2012-10-08 13:24:31 +02:00
hypertransport.c Clean up #ifs 2012-05-08 00:34:34 +02:00
Kconfig Hide all _ROM_RUN Kconfig options if the payload is SeaBIOS 2012-10-29 09:36:18 +01:00
Makefile.inc Every chip must have chip_operations 2012-10-08 13:24:31 +02:00
pci_device.c Clean up #ifs 2012-05-08 00:34:34 +02:00
pci_ops.c Various cosmetic and coding style fixes in src/devices. 2010-11-04 23:23:47 +00:00
pci_rom.c Clean up #ifs 2012-05-08 00:34:34 +02:00
pciexp_device.c Add support for enabling PCIe Common Clock and ASPM 2012-03-29 22:16:07 +02:00
pcix_device.c Various cosmetic and coding style fixes in src/devices. 2010-11-04 23:23:47 +00:00
pnp_device.c printf: Remove some L modifier uses 2012-03-24 15:32:24 +01:00
root_device.c Drop redundant CHIP_NAME in mainboard.c 2012-11-06 21:59:21 +01:00
smbus_ops.c Various cosmetic and coding style fixes in src/devices. 2010-11-04 23:23:47 +00:00