Sven Schnelle 0860e723cb udelay: add missing bus frequency ... commit 5b6404e419 ("Fix timer frequency detection on Sandybridge") reworked the udelay code, but didn't add the 333MHz FSB entry used on Model 15 Xeons. Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1099 Tested-by: build bot (Jenkins)		2012-06-12 10:01:16 +02:00
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16bit	Revert wbind added to the reset_vector	2012-04-20 09:09:42 +02:00
32bit	Remove whitespace.	2012-02-17 19:04:31 +01:00
cache	post code: Replaced hard-coded post code with macro	2012-01-23 22:50:56 +01:00
lapic	udelay: add missing bus frequency	2012-06-12 10:01:16 +02:00
mtrr	Fix the location of "Setting variable MTRR" printk.	2012-05-30 08:32:38 +02:00
name	Rename build system variables to be more intuitive, and	2010-09-30 16:55:02 +00:00
pae	drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed	2012-03-30 17:46:09 +02:00
smm	Add Sandybridge/Cougar Point support to SMM relocation handler	2012-04-06 02:15:34 +02:00
tsc	Rename build system variables to be more intuitive, and	2010-09-30 16:55:02 +00:00
fpu_enable.inc	Add a few missing license headers based on svn logs, and also add a	2010-09-27 17:53:17 +00:00
Kconfig	Add Kconfig options to enable TSEG and set a size	2012-03-30 17:47:22 +02:00
sse_enable.inc	Add a few missing license headers based on svn logs, and also add a	2010-09-27 17:53:17 +00:00