GNUBoot/coreboot-kgpe-d16
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coreboot-kgpe-d16/src/northbridge/intel/x4x
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Nico Huber 089b9089c1 nb/intel: Use postcar_frame_add_romcache() 
Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04 08:21:56 +00:00
..
acpi
acpi.c nb/x4x: Get rid of device_t 2018-04-30 09:22:32 +00:00
bootblock.c
chip.h
dq_dqs.c nb/intel/x4x: Implement write leveling 2018-05-24 13:03:45 +00:00
early_init.c nb/intel/x4x: Change memory layout to improve MTRR 2018-05-01 17:42:30 +00:00
gma.c northbridge/intel: Remove unneeded includes 2018-06-04 02:38:01 +00:00
iomap.h
Kconfig nb/intel/x4x: Use SPI flash to cache raminit results 2018-04-17 10:39:45 +00:00
Makefile.inc nb/intel/x4x: Rename a things that are not specific to DDR2 2018-05-14 07:40:49 +00:00
northbridge.c {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
ram_calc.c nb/intel: Use postcar_frame_add_romcache() 2018-06-04 08:21:56 +00:00
raminit.c nb/intel/x4x: Add DDR3 JEDEC init 2018-05-24 13:03:15 +00:00
raminit_ddr23.c nb/intel/x4x: Adapt post JEDEC for DDR3 2018-05-24 13:05:32 +00:00
raminit_tables.c nb/intel/x4x: Adapt post JEDEC for DDR3 2018-05-24 13:05:32 +00:00
rcven.c nb/intel/x4x/rcven.c: Change the verbosity of some messages 2018-04-17 10:41:57 +00:00
x4x.h nb/intel/x4x: Adapt post JEDEC for DDR3 2018-05-24 13:05:32 +00:00