8e3464109e
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
20 lines
484 B
Text
20 lines
484 B
Text
# Config file for the ThinCan dbe61
|
|
|
|
target dbe61
|
|
mainboard artecgroup/dbe61
|
|
|
|
# leave 64k for vsa
|
|
option CONFIG_COMPRESSED_ROM_STREAM=0
|
|
option ROM_SIZE=1024*256-64*1024
|
|
option FALLBACK_SIZE=ROM_SIZE
|
|
|
|
option DEFAULT_CONSOLE_LOGLEVEL = 11
|
|
option MAXIMUM_CONSOLE_LOGLEVEL = 11
|
|
romimage "fallback"
|
|
option USE_FALLBACK_IMAGE=1
|
|
option ROM_IMAGE_SIZE=32*1024
|
|
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
|
payload /tmp/rtl8139--filo.zelf
|
|
end
|
|
|
|
buildrom ./linuxbios.rom ROM_SIZE "fallback"
|