7146445be9
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2008-2009 coresystems GmbH
|
|
* Copyright (C) 2014 Google Inc.
|
|
* Copyright (C) 2015 Intel Corporation.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <arch/io.h>
|
|
#include <console/console.h>
|
|
#include <delay.h>
|
|
#include <device/device.h>
|
|
#include <device/pci.h>
|
|
#include <device/pci_def.h>
|
|
#include <soc/pch.h>
|
|
#include <soc/pci_devs.h>
|
|
#include <soc/ramstage.h>
|
|
|
|
u8 pch_revision(void)
|
|
{
|
|
return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID);
|
|
}
|
|
|
|
u16 pch_type(void)
|
|
{
|
|
return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
|
|
}
|
|
|
|
#if ENV_RAMSTAGE
|
|
void pch_enable_dev(device_t dev)
|
|
{
|
|
/* FSP should implement routines to disable PCH IPs */
|
|
u32 reg32;
|
|
|
|
/* These devices need special enable/disable handling */
|
|
switch (PCI_SLOT(dev->path.pci.devfn)) {
|
|
case PCH_DEV_SLOT_PCIE:
|
|
return;
|
|
}
|
|
|
|
if (!dev->enabled) {
|
|
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
|
|
|
|
/* Ensure memory, io, and bus master are all disabled */
|
|
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
|
reg32 &= ~(PCI_COMMAND_MASTER |
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
|
|
pci_write_config32(dev, PCI_COMMAND, reg32);
|
|
} else {
|
|
/* Enable SERR */
|
|
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
|
reg32 |= PCI_COMMAND_SERR;
|
|
pci_write_config32(dev, PCI_COMMAND, reg32);
|
|
}
|
|
}
|
|
|
|
#endif
|