7a1a3ad2ce
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
164 lines
4 KiB
C
164 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <timestamp.h>
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#include <cpu/x86/tsc.h>
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#include <elog.h>
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#include "pch.h"
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#include "chip.h"
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#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
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#include "lp_gpio.h"
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#else
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#include "southbridge/intel/common/gpio.h"
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#endif
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const struct rcba_config_instruction pch_early_config[] = {
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/* Enable IOAPIC */
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RCBA_SET_REG_16(OIC, 0x0100),
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/* PCH BWG says to read back the IOAPIC enable register */
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RCBA_READ_REG_16(OIC),
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RCBA_END_CONFIG,
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};
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int pch_is_lp(void)
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{
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u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
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return id == PCH_TYPE_LPT_LP;
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}
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static void pch_enable_bars(void)
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{
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/* Setting up Southbridge. In the northbridge code. */
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pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
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/* Enable ACPI BAR */
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pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80);
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pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
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/* Enable GPIO functionality. */
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pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
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}
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static void pch_generic_setup(void)
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{
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printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
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RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
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outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
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printk(BIOS_DEBUG, " done.\n");
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}
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uint64_t get_initial_timestamp(void)
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{
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tsc_t base_time = {
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.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
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.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
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};
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return tsc_to_uint64(base_time);
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}
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static int sleep_type_s3(void)
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{
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u32 pm1_cnt;
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u16 pm1_sts;
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int is_s3 = 0;
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/* Check PM1_STS[15] to see if we are waking from Sx */
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pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
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if (pm1_sts & WAK_STS) {
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/* Read PM1_CNT[12:10] to determine which Sx state */
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pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
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if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) {
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/* Clear SLP_TYPE. */
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outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
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is_s3 = 1;
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}
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}
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return is_s3;
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}
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void pch_enable_lpc(void)
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{
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const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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const struct southbridge_intel_lynxpoint_config *config = NULL;
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/* Set COM1/COM2 decode range */
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
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/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
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u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
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COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
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pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config);
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/* Set up generic decode ranges */
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if (!dev)
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return;
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if (dev->chip_info)
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config = dev->chip_info;
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if (!config)
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return;
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
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}
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int early_pch_init(const void *gpio_map,
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const struct rcba_config_instruction *rcba_config)
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{
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int wake_from_s3;
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pch_enable_lpc();
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pch_enable_bars();
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#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
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setup_pch_lp_gpios(gpio_map);
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#else
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setup_pch_gpios(gpio_map);
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#endif
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console_init();
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pch_generic_setup();
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/* Enable SMBus for reading SPDs. */
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enable_smbus();
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/* Early PCH RCBA settings */
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pch_config_rcba(pch_early_config);
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/* Mainboard RCBA settings */
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pch_config_rcba(rcba_config);
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wake_from_s3 = sleep_type_s3();
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#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
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if (!wake_from_s3)
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boot_count_increment();
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#endif
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/* Report if we are waking from s3. */
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return wake_from_s3;
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}
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