coreboot-kgpe-d16/src
Duncan Laurie fe86666913 intel/skylake: Clean up USB configuration in devicetree
Instead of having many different arrays for USB configuration,
with each array containing one bit of information, have one
array containing all the information for each port.

This way we can put the basic tuning parameters into a
structure and then define structures for the basic supported
configurations.

The existing port definitions are taken from the Skylake HSIO
tuning guide.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados, verify USB functionality in
all ports.

Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506
Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/306734
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12163
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:20:36 +01:00
..
acpi acpi/sata: add generic sata ssdt port generator 2015-06-07 01:24:47 +02:00
arch armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write 2015-10-17 18:10:29 +00:00
commonlib vboot: prepare for x86 verstage 2015-10-11 23:57:29 +00:00
console x86: add standalone verstage support 2015-10-14 17:07:52 +00:00
cpu cpu/amd/car: Add initial Suspend to RAM (S3) support 2015-10-27 15:12:08 +01:00
device yabel: explicitly cast values to match printk expectations 2015-10-25 07:29:55 +01:00
drivers FSP1_1: Always use common code 2015-10-27 15:19:23 +01:00
ec ec/chrome: Disable LPC Continuous Serial IRQ Select 2015-10-27 15:18:50 +01:00
include coreboot: make lb_framebuffer a weak function 2015-10-27 15:15:09 +01:00
lib boot_device: add call to boot_device_init() 2015-10-27 15:18:33 +01:00
mainboard intel/skylake: Clean up USB configuration in devicetree 2015-10-27 15:20:36 +01:00
northbridge northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendations 2015-10-27 05:31:57 +01:00
soc intel/skylake: Clean up USB configuration in devicetree 2015-10-27 15:20:36 +01:00
southbridge southbridge/amd/sr5650: Add AMD Family 15h CPU support 2015-10-26 07:32:58 +01:00
superio superio/nuvoton/nct5572d: Enable power state after power failure support 2015-10-23 20:04:07 +02:00
vendorcode amd/sb800: Make UsbRxMode per-board customizable 2015-10-24 00:21:01 +02:00
Kconfig Separate bootsplash image menuconfig option from others 2015-10-25 07:28:38 +01:00