78b6a1bbcd
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
46 lines
1 KiB
Text
46 lines
1 KiB
Text
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
|
|
#include <acpi/acpi.h>
|
|
#include <variant/ec.h>
|
|
|
|
DefinitionBlock(
|
|
"dsdt.aml",
|
|
"DSDT",
|
|
ACPI_DSDT_REV_2,
|
|
OEM_ID,
|
|
ACPI_TABLE_CREATOR,
|
|
0x20110725 // OEM revision
|
|
)
|
|
{
|
|
/* Some generic macros */
|
|
#include <soc/intel/common/acpi/platform.asl>
|
|
|
|
/* global NVS and variables */
|
|
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
|
|
|
/* CPU */
|
|
#include <cpu/intel/common/acpi/cpu.asl>
|
|
|
|
Scope (\_SB) {
|
|
Device (PCI0)
|
|
{
|
|
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
|
#include <soc/intel/alderlake/acpi/southbridge.asl>
|
|
}
|
|
}
|
|
|
|
/* Chipset specific sleep states */
|
|
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
|
|
|
/* Chrome OS specific */
|
|
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
|
|
|
/* Chrome OS Embedded Controller */
|
|
Scope (\_SB.PCI0.LPCB)
|
|
{
|
|
/* ACPI code for EC SuperIO functions */
|
|
#include <ec/google/chromeec/acpi/superio.asl>
|
|
/* ACPI code for EC functions */
|
|
#include <ec/google/chromeec/acpi/ec.asl>
|
|
}
|
|
}
|